Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 145
Bits Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
1: slave is disabled
NOTE: Software must ensure
slave and master mode are
mutually exclusive.
IMPORTANT:
if IC_SLAVE_DISABLE == 0 --
> MASTER_MODE == 0
5 RW 1'b1 Restart Support
(IC_RESTART_EN)
Determines whether RESTART
conditions may be sent when
acting as a master. Some
older slaves do not support
handling RESTART conditions;
however, RESTART conditions
are used in several I2C
controller operations.
0: disable
1: enable
When RESTART is disabled,
the master is prohibited from
performing the following
functions:
- Change direction within a
transfer (split)
- Send a START BYTE
- High-speed mode operation
- Combined format transfers in
7-bit addressing modes
- Read operation with a 10-bit
address
- Send multiple bytes per
transfer By replacing RESTART
condition followed by a STOP
and a subsequent START
condition, split operations are
broken down into multiple I2C
transfers. If the above
operations are performed, it
will result in setting TX_ABRT
of the IC_RAW_INTR_STAT
register
4 RW 1'b1 Master Addressing Mode
(IC_10BITADDR_MASTER)
Controls whether the I2C
controller starts its transfers in
7- or 10-bit addressing mode
when acting as a master.
0: 7-bit addressing
1: 10-bit addressing