Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
144 Document Number: 333577-002EN
Bits Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
31:1
0
RO 22'b0 Reserved (RSV)
9 RW 1'b0 RX_FIFO_FULL_HLD_CTRL
(RX_FIFO_FULL_HLD_CTRL
)
This bit controls whether the
bus should be held when the
Rx FIFO is physically full to its
RX_BUFFER_DEPTH, as
described
in the
IC_RX_FULL_HLD_BUS_EN
parameter.
Dependencies: This register
bit value is applicable only
when the
IC_RX_FULL_HLD_BUS_EN
configuration parameter is set
to 1. If
IC_RX_FULL_HLD_BUS_EN =
0, then this bit is read-only. If
IC_RX_FULL_HLD_BUS_EN =
1, then this bit can be read or
write.
8 RW 1'b0 TX_EMPTY_CTRL
(TX_EMPTY_CTRL)
This bit controls the
generation of the TX_EMPTY
interrupt, as described in the
IC_RAW_INTR_STAT register
7 RW 1'b0 STOP_DET_IFADDRESSED
(STOP_DET_IFADDRESSED
)
In slave mode:
1b1 issues the STOP_DET
interrrupt only when it is
addressed.
1b0 issues the STOP_DET
irrespective of whether its
addressed
or not.
6 RW 1'b1 Slave Mode Disable
(IC_SLAVE_DISABLE)
This bit controls whether I2C
has its slave disabled.
If this bit is set (slave
disabled), I2C controller
functions only as a master.
0: slave is enabled