Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
142 Document Number: 333577-002EN
• Hardware Handshake Interface to support DMA capability
• Interrupt Control
• FIFO support with 16B deep RX and TX FIFO’s
13.3 Memory Mapped IO Registers
Registers listed are for I2C 0, starting at base address B0002800h.
Table 31. Summary of I
2
C Registers—0xB0002800
MEM
Address
Default Instance Name Name
0xB0002800 0000_007Fh IC_CON Control Register
0xB0002804 0000_2055h IC_TAR Master Target Address
0xB0002808 0000_0055h IC_SAR Slave Address
0xB000280C 0000_0001h IC_HS_MADDR High Speed Master ID
0xB0002810 0000_0000h IC_DATA_CMD Data Buffer and Command
0xB0002814 0000_0190h IC_SS_SCL_HCNT Standard Speed Clock SCL High Count
0xB0002818 0000_01D6h IC_SS_SCL_LCNT Standard Speed Clock SCL Low Count
0xB000281C 0000_003Ch IC_FS_SCL_HCNT Fast Speed Clock SCL High Count
0xB0002820 0000_0082h IC_FS_SCL_LCNT Fast Speed I2C Clock SCL Low Count
0xB0002824 0000_0006h IC_HS_SCL_HCNT High Speed I2C Clock SCL High Count
0xB0002828 0000_0010h IC_HS_SCL_LCNT High Speed I2C Clock SCL Low Count
0xB000282C 0000_0000h IC_INTR_STAT Interrupt Status
0xB0002830 0000_18FFh IC_INTR_MASK Interrupt Mask
0xB0002834 0000_0000h IC_RAW_INTR_STAT Raw Interrupt Status
0xB0002838 0000_000Fh IC_RX_TL Receive FIFO Threshold Level
0xB000283C 0000_0000h IC_TX_TL Transmit FIFO Threshold Level
0xB0002840 0000_0000h IC_CLR_INTR Clear Combined and Individual Interrupt
0xB0002844 0000_0000h IC_CLR_RX_UNDER Clear RX_UNDER Interrupt
0xB0002848 0000_0000h IC_CLR_RX_OVER Clear RX_OVER Interrupt
0xB000284C 0000_0000h IC_CLR_TX_OVER Clear TX_OVER Interrupt
0xB0002850 0000_0000h IC_CLR_RD_REQ Clear RD_REQ Interrupt
0xB0002854 0000_0000h IC_CLR_TX_ABRT Clear TX_ABRT Interrupt
0xB0002858 0000_0000h IC_CLR_RX_DONE Clear RX_DONE Interrupt