Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 141
13 I
2
C
The SoC implements one instance of an I
2
C controller, which can operate in master
mode or slave mode as configured. Both 7 bit and 10 bit addressing modes are
supported.
13.1 Signal Descriptions
Please see Chapter 2, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O
(bidirectional)
• Type: The buffer type found in Chapter 4, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 30. Memory 0 Signals
Signal Name Direction/
Type
Description
I2C_0_CLK I/O I2C Serial Clock:
I2C_0_DATA I/O I2C Serial Data:
The following is a list of the I
2
C features:
13.2 Features
• One I
2
C Interface
• Support both Master and Slave operation
• Operational Speeds:
o Standard Mode (0 to 100 Kbps)
o Fast Mode (≤ 400 Kbps)
o Fast Mode Plus (≤ 1 Mbps)
• 7 bit or 10 bit Addressing
• Supports Clock Stretching by Slave Devices
• Multi-Master Arbitration
• Spike Suppression