Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 131
Bits Access
Type
Default Description PowerWell
23:20 RW/L 4'h0 RD_ALLOW (RD_ALLOW)
Enable Read Access on an Agent by Agent
basis:
[0] : Enables Read Access for the Host
Processor
[1] : Reserved
[2] : Enables Read Access for DMA
[3] : Reserved
19:18 RO 2'h0 RSV1 (RSV1)
Reserved
17:10 RW/L 8'h0 UPR_BOUND (UPR_BOUND)
Upper 2 address bits of this register are
unused by HW.
The Upper Address Bound is compared with
incoming Flash Address [15:10] to determine
the upper 1KB aligned value of the Protected
Region. For address comparison purposes,
lower bits[9:0] are assumed to be all 1’s.
Hence, incoming address is checked to be
less than or equal to this field.
9:8 RO 2'h0 RSV (RSV)
Reserved
7:0 RW/L 8'h0 LWR_BOUND (LWR_BOUND)
Upper 2 address bits of this register are
unused by HW.
The Lower Address Bound is compared with
incoming Flash Address [15:10] to determine
the lower 1KB aligned value of the Protected
Region. For address comparison purposes,
lower bits[9:0] are assumed to be all 0’s.
Hence, incoming address is checked to be
greater than or equal to this field.
12.4.2.12 MPR_WR_CFG (MPR_WR_CFG)
Flash Write Protection Control Register
This register is unused in HW and serves no purpose.
MEM Offset (B0100000) 2Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h