Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
124 Document Number: 333577-002EN
12.4.2.4 FLASH_WR_CTRL (FLASH_WR_CTRL)
Flash Write Control Register
Before issuing flash erase/program operation,
1. FW must disable all interrupts except the flash interrupt that indicates completion
of erase/program operation.
2. Issue the MMIO write that triggers the program or erase operation.
3. Issue HALT instruction.
As part of program/erase completion ISR, interrupts can be re-enabled.
MEM Offset (B0100000) 0Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:26 RO 6'h0 RSV (RSV)
Reserved
25 RW 1’b0 INTR_EN_ER
Enable interrupt after Erase completion. This
bit has no effect on ER_DONE status bit.
24 RW 1’b0 INTR_EN_WR
Enable interrupt after Program cycle
completion. This bit has no effect on
WR_DONE status bit.
23:20 RO 4’b0 RSV (RSV)
Reserved
19:2 RW 18'b0 WR_ADDR (WR_ADDR)
Write Address
Upper 2 address bits are unused by HW. So,
SW must ensure there is no address aliasing.
Address must be in Flash Physical Address
Space.
1 RW/V 1'b0 ER_REQ (ER_REQ)
Erase request - set to '1' to trigger a Flash
Page Erase. The page number is specified by
WR_ADDR[17:11]. ER_REQ is self clearing.
ER_REQ has no effect after CTRL.FL_WR_DIS
has been written to '1'.
0 RW/V 1'b0 WR_REQ (WR_REQ)
Write request - set WR_REQ to '1' to trigger a
Flash write. Check the
FLASH_STTS.WR_DONE bit to determine
when the write completes. WR_REQ is self
clearing. WR_REQ has no effect after
CTRL.FL_WR_DIS has been written to '1'.