Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
122 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell
9:6 RW 4'h1 READ_WAIT_STATE_L
(READ_WAIT_STATE_L)
Flash SE low pulse width in system clocks
plus one. This must be set to one when the
system clock frequency is above 20 MHz. This
determines when the Flash controller
generates a read data valid indication and is
based on the Flash data access time.
5:0 RW 6'h20 MICRO_SEC_CNT (MICRO_SEC_CNT)
Number of clocks in a micro second.
12.4.2.2 ROM_WR_CTRL (ROM_WR_CTRL)
ROM Write Control Register
This register is only applicable for 8KB OTP region. There is no equivalent register for
4KB OTP region.
Before issuing flash erase/program operation,
1. FW must disable all interrupts except the flash interrupt that indicates completion
of erase/program operation.
2. Issue the MMIO write that triggers the program or erase operation.
3. Issue HALT instruction.
As part of program/erase completion ISR, interrupts can be re-enabled.
MEM Offset (B0100000) 4h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:20 RO 12'h0 RSV (RSV)
Reserved
19:2 RW 18'b0 WR_ADDR (WR_ADDR)
Write Address
Upper 2 address bits are unused by HW. SW
must ensure there is no address aliasing.
Address must be in Flash Physical Address
Space.