Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 121
12.4.2 Flash Controller 0 Register Detailed Description
12.4.2.1 TMG_CTRL (TMG_CTRL)
Flash Timing Control Register. There is a SW programming restriction for this register.
When switching SoC to a higher frequency, this register must be updated first to
reflect settings associated with higher frequency BEFORE SoC frequency is changed.
On the other hand, when switching SoC to a lower frequency, this register must be
updated only 6 NOP instructions AFTER the SoC frequency has been updated.
Otherwise, flash timings will be violated.
READ_WAIT_STATE_L and MICRO_SEC_CNT are optimized for 32MHz. These settings
are conservative for lower frequency and add access latency for reads. But
functionally, these settings will work for any frequency <= 32MHz for reads. For
program/erase operations, default value of MICRO_SEC_CNT will violate flash timings
at < 32MHz frequency. Hence, MICRO_SEC_CNT must be changed before flash can be
programmed/erased at non-32MHz frequency.
MEM Offset (B0100000) 0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0060h
Bits Access
Type
Default Description PowerWell
31:15 RO 17'h0 RSV (RSV)
Reserved
14 RW 1'h0 CLK_SLOW (CLK_SLOW)
Slow clock - when 1 , zero wait state flash
access is possible. When 0 , flash accesses
will always have one or more wait states. This
bit must be set to zero when clock
frequencies are above 6.7 MHz.
13:10 RW 4'h0 READ_WAIT_STATE_H
(READ_WAIT_STATE_H)
Upper bit (i.e. bit 13) is
32MHz_Exit_Latency_Opt
Setting of this bit reduces the potential 128
clock latency. FW is expected to set this bit
during boot.
Remaining 3 bits: Flash SE high pulse width
in system clocks plus one. Set to 0 for clock
frequencies below 66MHz.