Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
120 Document Number: 333577-002EN
Since AHB write to above register fields can be concurrent to ITCM code fetches, some
form of synchronization is required to ensure ITCM interface is quiesced for these
registers to alter SoC operation in a safe manner. It is possible to analyze the above 3
cases and find solutions. But a capability to control ITCM prefetching under specific
conditions is a very useful capability that is lacking. One of the solutions is to execute
HALT instruction as a following instruction that updates above register fields. Upon
completion of HALT instruction, LMT is guaranteed to have made all interfaces idle. The
assertion of xhalt signal (output of LMT) can be used as a deterministic mechanism to
take effect the new states of registers like above.
12.4 Memory Mapped IO Registers
This section describes IO registers.
12.4.1 Flash Controller 0 Register Summary
MEM BaseAddress: 0xB0100000
MEM
Address
Default Name Description
0x0 0000_0060h TMG_CTRL TMG_CTRL
0x4 0000_0000h ROM_WR_CTRL ROM_WR_CTRL
0x8 0000_0000h ROM_WR_DATA ROM_WR_DATA
0xC 0000_0000h FLASH_WR_CTRL FLASH_WR_CTRL
0x10 0000_0000h FLASH_WR_DATA FLASH_WR_DATA
0x14 0000_0000h FLASH_STTS FLASH_STTS
0x18 0000_0000h CTRL CTRL
0x1C 0000_0000h FPR0_RD_CFG FPR0_RD_CFG
0x20 0000_0000h FPR1_RD_CFG FPR1_RD_CFG
0x24 0000_0000h FPR2_RD_CFG FPR2_RD_CFG
0x28 0000_0000h FPR3_RD_CFG FPR3_RD_CFG
0x2C 0000_0000h MPR_WR_CFG MPR_WR_CFG
0x30 0000_0000h MPR_VSTS MPR_VSTS
0x34 CCCC_CCCCh MPR_VDATA MPR_VDATA