Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
12 Document Number: 333577-002EN
21.1 Signal Descriptions ............................................................................. 380
21.2 Features ........................................................................................... 381
21.3 Use .................................................................................................. 381
22 Analog to Digital Convertor (ADC) ................................................................... 383
22.1 Signal Descriptions ............................................................................. 383
22.2 Features ........................................................................................... 383
22.3 Use .................................................................................................. 384
22.4 Memory Mapped IO Registers ............................................................... 386
22.4.1.1 ADC Channel Sequence Table (ADC_SEQ [0..7]) ......... 386
22.4.1.2 ADC Command Register (ADC_CMD) ......................... 388
22.4.1.3 ADC Interrupt Status Register (ADC_INTR_STATUS) .... 390
22.4.1.4 ADC Interrupt Enable (ADC_INTR_ENABLE) ................ 391
22.4.1.5 ADC Sample Register (ADC_SAMPLE) ........................ 392
22.4.1.6 ADC Calibraton Data Register (ADC_CALIBRATION) ..... 392
22.4.1.7 ADC FIFO Count Register (ADC_FIFO_COUNT) ............ 393
22.4.1.8 ADC Operating Mode Register (ADC_OP_MODE) .......... 393
23 Interrupt Routing .......................................................................................... 395
23.1 Interrupt Routing ............................................................................... 395
23.1.1 Host Processor Interrupts ....................................................... 395
23.1.2 SoC Interrupts and Routing .................................................... 396
24 System Control Subsystem ............................................................................. 398
24.1 Features ........................................................................................... 398
24.2 Memory Mapped IO Registers ............................................................... 399
24.3 Register Detailed Description ............................................................... 402
24.3.1.1 Hybrid Oscillator Configuration 0 (OSC0_CFG0) ........... 402
24.3.1.2 Hybrid Oscillator status 1 (OSC0_STAT1) ................... 405
24.3.1.3 Hybrid Oscillator configuration 1 (OSC0_CFG1) ........... 406
24.3.1.4 RTC Oscillator status 0 (OSC1_STAT0) ....................... 408
24.3.1.5 RTC Oscillator Configuration 0 (OSC1_CFG0) .............. 409
24.3.1.6 Peripheral Clock Gate Control
(CCU_PERIPH_CLK_GATE_CTL) ................................ 410
24.3.1.7 Peripheral Clock Divider Control 0
(CCU_PERIPH_CLK_DIV_CTL0) ................................. 413
24.3.1.8 Peripheral Clock Divider Control 1
(CCU_GPIO_DB_CLK_CTL) ....................................... 414
24.3.1.9 External Clock Control Register
(CCU_EXT_CLOCK_CTL) .......................................... 415
24.3.1.10 System Low Power Clock Control (CCU_LP_CLK_CTL) .. 416
24.3.1.11 Wake Mask register (WAKE_MASK) ........................... 418
24.3.1.12 AHB Control Register (CCU_MLAYER_AHB_CTL) .......... 419
24.3.1.13 System Clock Control Register (CCU_SYS_CLK_CTL) .... 420
24.3.1.14 Clocks Lock Register (OSC_LOCK_0) ......................... 421
24.3.1.15 SoC Control Register (SOC_CTRL) ............................. 423
24.3.1.16 SoC Control Register Lock (SOC_CTRL_LOCK) ............. 424
24.3.1.17 General Purpose Sticky Register 0 (GPS0) .................. 424
24.3.1.18 General Purpose Sticky Register 1 (GPS1) .................. 425
24.3.1.19 General Purpose Sticky Register 2 (GPS2) .................. 425
24.3.1.20 General Purpose Sticky Register 3 (GPS3) .................. 425
24.3.1.21 General Purpose Scratchpad Register 0 (GP0) ............. 426
24.3.1.22 General Purpose Scratchpad Register 1 (GP1) ............. 426
24.3.1.23 General Purpose Scratchpad Register 2 (GP2) ............. 426