Datasheet
Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
116 Document Number: 333577-002EN
• All DTCM writes and UC AHB reads (data accesses) must be in
program order.
• Same as A3 and A4 above except replace AHB write with AHB
read.
• AHB reads that are code accesses (e.g. to SRAM) have no
ordering relationship with DTCM writes.
Inside LMT, there is only a single data access outstanding at any
time
• Flash Memory & Flash Controller:
o Flash controller has 2 interfaces: ITCM and AHB Slave.
o Flash Memory has asynchronous interface i.e. there is no clock input.
o Read from embedded Flash memory is similar to a standard SRAM read but
with increased latency.
o However, there is no write capability to Flash memory that is equivalent to
a standard SRAM write.
o Flash allows a 32b write to arbitrary location (Program Operation) that takes
~40us (36KB Flash Memory size). There is an optional interrupt generation
capability after write completion. However, only a ‘1’ in a cell can be
changed to a ‘0’ during a Program operation. The only mechanism to write
a ‘1’ to a location is to perform a Page–erase operation (2KB page size in
Intel
®
Quark™ microcontroller D2000) or a Mass erase operation which
erases entire flash contents to all 1’s. An erase operation lasts for ~20ms
duration. There is an optional interrupt generation capability after erase
completion.
o A Program operation is performed via a sequence of writes to Flash
Configuration registers.
Write target 32b data content to a register
Write target flash address to a register
Write to a bit in a control register that triggers the required Program
sequence operation.
o Flash Configuration registers reside off of AHB fabric sharing the AHB Slave
port with Flash Controller/Memory.
o There is also an upper bound on how many program operations can be
performed to same cell - in between erases.
o Flash Memory has a single port and only a single operation can be performed
at a time. During flash program or erase operation, flash memory is not
accessible during the entire duration.
o The AHB Slave port has no write-posting capability.
o Flash latency can be changed to optimize latency for different clock
frequencies.
• SRAM & SRAM Controller:
o SRAM controller has 2 interfaces: DTCM and AHB Slave.
o Standard SRAM reads and writes
o SRAM Configuration registers reside off of AHB fabric sharing the AHB Slave
port with SRAM Controller/Memory.
o The AHB Slave port and DTCM interface have no write-posting capability.
• AHB/APB Fabric
o No write posting support i.e. all writes are non-posted.
o In-order fabric with no pipelining.
o Only 2 masters on fabric: LMT and DMA.