Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 115
• Wait-state capability
• Fastest access limited by eFlash latency: 2 wait-state @
32MHz
 64b DTCM: Data TCM
• Address range hardwired – see LMT-ULP Address Map later
• Reads/Writes to DTCM address range
• Wait-state capability
 32b AHB-Lite: Peripheral interface
• Master on AHB Lite interface
• No AHB Slave port
• No bursting capability
• Code Reads to DTCM address range
• Data reads/writes to ITCM address range
• All probe mode accesses are issued on AHB
• I/O reads/writes are unsupported by the Intel
®
Quark™
microcontroller D2000. Such transactions are under SW
control and aliased to Memory range on AHB-Lite.
• All transactions are non-posted transactions.
• Atomic/Locked transactions are issues as regular memory
transactions without lock semantics.
o IO(x)APIC + LAPIC
 32 IRQs
o Memory Ordering Model
 Processor Ordered Memory model
 DTCM reads are allowed to go ahead of writes (to different
addresses than reads)
 All AHB transactions are in program order.
 Transactions across ITCM and DTCM interfaces have no ordering
relationship to each other.
 Transactions across ITCM and AHB-Lite interfaces have no ordering
relationship to each other. In other words, ITCM read transactions
can occur concurrently with AHB-Lite reads/writes.
 All Stores in LMT must be in program order. It implies:
• Writes on DTCM interface must be in program order.
• Writes on AHB Lite interface must be in program order.
• DTCM write (data access) followed by AHB write (data
access) must be in program order.
o Specifically, the AHB write cannot start until DTCM
write completes. An implication of this is that if SoC
introduces wait-states on DTCM interface for the
write, LMT will not start the AHB write until the
DTCM write completes i.e. wait state goes away and
SRAM controller accepts the write.
• AHB write (data access) followed by DTCM write (data
access) must be in program order.
• Similar to previous case. The DTCM write cannot start
until AHB write completes. An implication of this is that
if SoC introduces wait-states on AHB-Lite interface for
the write, LMT will not start the DTCM write until the
AHB write completes i.e. AHB fabric gives a response
for the write.