Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
114 Document Number: 333577-002EN
12.3 Memory Consistency Analysis
The following illustration is the block diagram of the memory subsystem.
Figure 11 Block Diagram of The Memory Subsystem
Peripherals
DMA
AHB Fabric
(Multi-Layer)
Lakemont ULP
Host Processor
(No L1 cache)
8kB
SRAM
Data TCM I/F
AHB I/F
32bit
AHB Sla ve
TCM I/F
64bit
AHB
Maste r
Periph Access
AHB
Slave
AHB
Maste r
SRAM
Arbiter /
Controller
AHB Sla ve
Flash
Controller
+ Arbitor
On-Die
Flash (32kB + 8KB
OTP + 4KB OTP)
AHB I/F
32
TCM I/F
64b
Instr TCM I/F
Flash Config Registers
SRAM Config Registers
Peripherals
AHB
Slave
Prefetcher
SCSS (SoC Clock/PM) Config
Registers
AHB Sla ve
From memory consistency analysis perspective, Intel
®
Quark™ microcontroller D2000
consists of following key IPs:
1. ULP Quark CPU core
2. Flash Memory & Flash Controlller
3. SRAM & SRAM Controlller
4. AHB/APB Fabric
5. DMA
6. Slave Peripherals
7. SCSS Configuration Registers
• LMT-ULP:
o Pentium x86 ISA
o No I$ or D$ and hence no need for snoops.
o 32b Addressing
o C0, C1 and C2 power states
o No FPU
o No support for Atomic operations
o 3 key interfaces:
 64b ITCM: Instruction TCM
• Address range hardwired – see LMT-ULP Address Map later
• Code Reads to ITCM address range
• Aggressive prefetcher for instruction fetches