Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 113
• Case 2: CPU executing from 0x1FFF (end of OTP Instruction ROM). CPU prefetch
can spill over to the reserved range 0x2000-0x7_FFFF.
o The accesses to the reserved range will be completed. The SoC will return
a fixed value of all Cs.
o This will NOT be treated as an error condition and No spurious interrupts
will be sent to the CPU.
• Case 3: CPU executing from 0x18_7FFF (end of Instruction RAM). CPU prefetch
can spill over to the reserved range 0x18_8000-0x1F_FFFF.
o The accesses to the reserved range will be completed. The SoC will return
a fixed value of all Cs.
o This will NOT be treated as an error condition and No spurious interrupts
will be sent to the CPU.
• Case 4: CPU executing from 0x20_0FFF (end of Data ROM). CPU prefetch can spill
over to the reserved range 0x20_1000-0x27_FFFF.
o The accesses to the reserved range will be completed.
o Since Data ROM access are sent out on AHB. The AHB fabric will return an
error and can inject an interrupt for error notification.
• Case 5: CPU executing from 0x28_1FFF (end of Data RAM). CPU prefetch can spill
over to the reserved range 0x28_2000-0x2F_FFFF.
o The accesses to the reserved range will be completed. The SoC will return
a fixed value of all Cs.
o Instruction fetches to the Data RAM are sent out on AHB Interface. The
AHB fabric will return an error and can inject an interrupt for error
notification.
• Case 6: CPU executing from a specific region of Data RAM which is setup via IMR
(Isolated Memory Region) registers such that CPU has privileges to execute from
that region. CPU prefetch can spill over to adjacent region for which CPU does not
have privileges to execute.
o The accesses to violated region will complete.
o Instruction fetches to the Data RAM are sent out on AHB Interface. SRAM
controller will flag an Access Control violation and can inject an interrupt
for error notification.
For cases 4, 5 and 6, the recommendation is for firmware to place the code at the
start of the Data RAM to avoid these scenarios and the potential spurious interrupts.