Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
112 Document Number: 333577-002EN
Scenario Notification
Event
Event Logging Data Handling
DTCM Out of Range
Read
None None Read data returned is 32b
value from register
duplicated in lower and
upper DW.
DTCM Read Access
Violation
Interrupt Agent, QW Address
(bit2 undefined),
Type.
Violations from DTCM
and AHB are mutually
exclusive.
Read data returned is 32b
value from register.
DTCM Out of Range
Write
None None Write data sent to SRAM
with inactive BEs.
DTCM Write Access
Violation
Interrupt Agent, QW Address
(bit2 undefined),
Type.
Violations from DTCM
and AHB are mutually
exclusive.
Read data returned is 32b
value from register
duplicated in lower and
upper DW. Write data sent
to SRAM with inactive BEs.
AHB Out of Range
Read/Write towards
SRAM
None. None None. AHB fabric will not
decode to SRAM.
AHB Read Access
Violation to SRAM
Interrupt Agent, DW Address
(bit2 undefined),
Type.
Violations from DTCM
and AHB are mutually
exclusive.
Read data returned is 32b
value from register.
AHB Write Access
Violation to SRAM
Interrupt Agent, DW Address
(bit2 undefined),
Type.
Violations from DTCM
and AHB are mutually
exclusive.
Write data sent to SRAM
with inactive BEs.
Behavior of CPU prefetch crossing address boundaries is as follows:
• Case 1: Reset vector fetch from 0xFFFF_FFF0 and 0xFFFF_FFF8 can potentially
cause the CPU to prefetch from address 0x0, 0x8 and 0x10
o The accesses to 0x0, 0x8, and 0x10 fall in the OTP code region. SoC will
return the data from the OTP ROM.
o This will NOT be treated as an error condition and No spurious interrupts
will be sent to the CPU.