Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 109
12.1.3 Internal SRAM Features
- The internal SRAM controller presents 8KB of SRAM – organized in the form of
2 banks of 4KB each.
- Supports 64 bit wide reads and writes via a dedicated Host Processor DTCM
Interface. Processor only reads and writes 32b at a time. Byte enables indicate
which SRAM bank the request is targeting. All accesses are 64b address
aligned.
- Supports 32 bit wide reads and writes via an AHB Lite Interface.
- A Rotated Priority access scheme is used to arbitrate between the DTCM
Interface and the AHB Lite Interface. The arbitration scheme will result in 0
wait states being applied to the respective interface for arbitration win
scenario and 1 wait state being applied to the respective interface for
arbitration loss scenario.
- Latency:
Clock Frequency DTCM Latency AHB Latency
All frequencies 0 wait-state 1 wait-state
Memory Region Protection capabilities are provided by the SRAM controller and apply
to accesses originating from both the TCM I/F block and the AHB I/F block. These
capabilities are as follows:
• 2 Agents:
o Lakemont Data TCM + Lakemont AHB (determined by the AHB Master
ID)
o DMA
• 4 Configurable Isolated Memory Regions (IMRs) for memory protection with
addressing of 1KB byte granularity
• The IMRs are defined by a lower bound and an upper bound, for an address to
be within the IMR it must be greater than or equal to the lower bound and
less than or equal to the upper bound
• The IMRs are disabled by default – in this case all Agents have RD & WR
access to the whole of the SRAM
• Each IMR has a set of programmable Access Control flags described as
follows:
MPR Enable LMT RD Access
Enable
DMA RD Access
Enable
LMT WR Access
Enable
DMA WR Access
Enable
• The Access Control flags can be locked – when locked they can only be re-
programmed after a Warm Reset
• The Regions may overlap refer to Figure 9 Example IMR zones – Requests that
fall in the region overlapped by IMR B and IMR C are only allowed if the
requesting agent is enabled for both IMRs
• In the event of an Access Violation during a Write Access the data is dropped,
not written to SRAM and the I/F protocol is handled as for a normal Write
Access (the byte enables can be brought low to satisfy this)
• In the event of an Access Violation during a Read Access the data is replaced
with Dummy Data, and the I/F protocol is handled as for a normal Read
Access (the read to SRAM can still be done to satisfy this with the dummy
data over-riding the actual data read from SRAM)
o This Dummy Data is programmable and is locked along with the
Access Control flags above.