Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 107
o Clk = 8MHz => 1 wait state on all accesses
o Clk = 16MHz => 1 wait state on all accesses
o Clk = 32MHz => 2 wait states on all accesses
Clock Frequency ITCM Latency AHB Latency
32MHz 2 wait-states 2 wait-states
8-16MHz 1 wait-state 2 wait-states
<= 4MHz 0/1 wait-state 1 wait-state
Flash Protection mechanisms: The Flash Read Protection features are as follows:
• There are 2 Agents:
o Lakemont (determined by the AHB Master ID)
o DMA (determined by the AHB Master ID)
 Protection mechanism s are the same between the 2 DMA
channels.
• Supports a lock-out feature where Flash writes/erases are disabled via a
register write. Once Flash writes have been disabled, a warm reset is required
to re-enable write access.
• 4 Configurable Flash Protection Regions (FPRs) with addressing of 1KB byte
granularity. There is no size restriction for each region. Each region has lower
and upper bound addresses - aligned to 1KB boundary, for address range
checks. Address used for comparison is offset within 36KB of Main Memory
block. With 1KB alignment, only 6b are needed for lower and upper bound
address comparison. The mechanism is not applicable to 8KB OTP Code region
of system address space.
• The FPRs are disabled by default – in this case all Agents have RD & WR
access to the whole of the Flash
• Each FPR has a set of programmable Access Control flags described as
follows:
FPR
Enable
LMT RD
Access
Enable
DMA RD
Access
Enable
• The Access Control flags can be locked – when locked they can only be re-
programmed after a Warm Reset
• The Regions may overlap – in this scenario ALL of the relevant Access Enables
needs to be set to allow an Agent to access that overlapping region (i.e. an
AND operation)
• In the event of an Access Violation during a Read Access the data is replaced
with value from a config register, and the I/F protocol is handled as for a
normal Read Access (the read to Flash is still performed and the read data
from Flash is overwritten)
• When an Access Violation occurs, a Violation Event trigger (Interrupt) is
asserted and the following information is logged: The Agent, the Address
(offset within 36KB Main Memory block) and the Transfer Type (Flash RD)
• There are 2 modes for handling a Violation Event:
o Debug Mode – the Violation Event is used to trigger Probe Mode on
Processor effectively triggering a break point -
o Normal Mode – the Violation Event is treated as an Interrupt that can
be routed to the Processor.