Datasheet

Memory Subsystem
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
106 Document Number: 333577-002EN
12 Memory Subsystem
The memory subsystem contains the following volatile and non-volatile memories:
- System Flash – 32KB
- OTP (implemented using Flash Memory) – 8KB + 4 KB
- Internal System SRAM – 8KB
Each of these regions implement protection mechanisms with access control described
later.
12.1 Features
12.1.1 System Flash Controller Features
- The Flash controller interfaces with 32KB Main Memory Block and 8KB of
Information Block of Flash memory.
- Supports 64b wide reads via a dedicated Host Processor ITCM Interface.
- Supports 32b wide Instruction reads via an AHB Lite interface. The 32b reads
can be performed as single read, incrementing burst or wrapping burst.
- Supports prefetching of programmable number (up to 4) 16B chunks from
Flash for requests from AHB interface – prefetching can be enabled/disabled
via a configuration register as part of Flash subsystem. There is no prefetching
performed on ITCM interface since Processor has its own internal prefetcher.
- Supports page erase via configuration registers in the System Control Module
- Each page is 2KB.
- Supports 32b wide writes via configuration registers in the System Control
Module. The procedure for updating Flash is as follows:
o Copy Flash Page, with location to be modified, to SRAM
o Erase the Flash page
o Update the relevant bytes in the SRAM copy
o Copy the modified page in SRAM into Flash
- Each 32b write operation takes approx. 40us (refer to Flash datasheet –
Tnvs(5us) + Tpgs(10us) + Tprog(20us) + Tnvh(5us)). Supports optional
interrupt generation capability after write completion.
- Supports mass erase via configuration registers in the System Control Module.
o Only when 4KB OTP has not been programmed. It is the responsibility
of FW to prevent Mass Erase when 4KB OTP has been programmed.
HW has no built-in protection.
o Supports optional interrupt generation capability after erase
completion.
- Supports erase reference cell via configuration in the System Control Module –
this needs to be done to allow reads to work – only needs to be done once in
the lifetime of the device.
- Support configurable wait states to allow Flash to run with different frequency
clocks. Number of wait states on Flash Read Access as follows:
o Clk = 4MHz or slower => 0 wait states supported on first access, 1
wait state on a subsequent access if the second access is on the next
clock, 0 wait states on a subsequent access if there is at least a single
clock cycle gap after the first access