Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 103
2. The latency for the first interrupt is close to what original LMT has. The latency to
deliver subsequent interrupt of the same vector is much improved. The microcode
latency is reduced to 21 cycles from 65 cycles.
a. This optimization is only enabled in protected ring0 flat mode.
i. CS, DS and SS base is 0 and corresponding limits are FFFF_FFFF
b. This optimization employs an 32-entry look-aside table
i. Entry 0 maps to external interrupt line 0 (vector 32), Entry 1
maps to external interrupt line 1 (vector 33), and so on
ii. Each entry contains a valid bit and EIP to corresponding
interrupt service routine.
iii. EIP to the start of ISR is captured into the interrupt-vector
lookaside buffer upon successful delivery of interrupt.
c. Invalidation of the interrupt-lookaside buffer is done when :
i. LGDT or LIDT instruction is executed
ii. Transition to non ring0
iii. When the following EFLAGS bits are set: VM, NT, RF and TF
d. ISR EIP will not be buffered for the following cases. Therefore, the slow
interrupt delivery path will be taken if SW does the following
i. ISR uses a different CS selector than the CS selector used by
the running program that is being interrupted.
ii. If the start of ISR is located outside of ITCM Instruction Flash
range, i.e. 0x0018_0000 to 0x0018_7FFF.
iii. Running in real mode and not in protected mode. In real mode,
the IDT is located starting at 0x0000_0000 address.
e. SW should use interrupt gate in IDT for ISR. Trap gates for ISR is not
supported
f. SW should not use 16-bit segment
g. All processes running at ring-0 level and allowing interrupts should use
the same pair of segments to address instructions and data to take
advantage of interrupt fastpath.
3. Requirement:
a. If FW modifies IDT or GDT after LIDT or LGDT, FW must execute LIDT
or LGDT again.
b. If SW wants to use “IRET/far call/far jmp” to change CS and thus
descriptor, SW needs to execute LGDT or LIDT to invalidate interrupt-
vector lookaside buffer first.
c. SW shall not place the start of ISR in the lowest 256 bytes, i.e.
0x0000_0000 to 0x0000_00FF.