Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
102 Document Number: 333577-002EN
• SW can also read the index from the IOREGSEL register through the same bits
1,2,3,5 and 6.
31
0
34567
Reserved
1
• The IOWIN register has 2 bits per interrupt line (index)
o Bit 15 : Trigger
o Bit 16 : Mask
31
0
14
Reserved
17
16 15
M T
Reserved
• Trigger: Software sets this bit to configure the interrupt signal as level sensitive.
Software clears this bit to configure the interrupt signal as edge sensitive.
• Mask: Software sets this bit to mask the interrupt signal and prevent the MVIC
from delivering the interrupt. The MVIC ignores interrupts signaled on a masked
interrupt pin and does not deliver nor hold the interrupt pending. Changing the
mask bit from unmasked to masked after the MVIC accepts the interrupt has
no effect on that interrupt. When this bit is 0, the MVIC does not mask the
interrupt and results in the eventual delivery of the interrupt.
• At reset, all interrupts are unmasked.
11.4.2 Programming Sequence
1. Initialize GDT
2. Initialize IDT
3. Initialize MVIC
a. Program the respective MVIC registers.
b. Program the mask and trigger mode for the 32 interrupt lines through
the I/O registers.
4. Enables Interrupts to flow (sti)
11.4.3 Interrupt Latency Reduction
1. One INTA is issued per interrupt
a. LMT-FST issues two INTA cycles
b. Validation infrastructure updates required