Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 101
11.4.1.8 ICR
• The initial count of the timer. The timer counts down from this value to 0.
• In periodic mode, the timer automatically reloads the Current Count Register (CCR)
from the ICR when the count reaches 0. At this time, the MVIC generates a timer
interrupt to the core and the countdown repeats.
• If during the countdown process software writes to the ICR, counting restarts using
the new initial count value.
• A write of 0 to the ICR effectively stops the local MVIC timer, in both one-shot and
periodic mode.
o The LVT Timer Register determines the vector number delivered to the core
when the timer count reaches zero.
o Software can use the mask flag in the LVT timer register to block the timer
interrupt.
31
0
Initial Count
11.4.1.9 CCR
• The current count of the timer.
31
0
Current Count
• Interrupt lines can be masked/unmasked and the sensitivity (level/edge) can be set
by programming the registers found in the I/O controller registers
Software accesses the registers by an indirect addressing scheme using two memory
mapped registers, IOREGSEL and IOWIN. Only the IOREGSEL and IOWIN registers are
directly accessible in the memory address space. To setup an interrupt, software writes
to IOREGSEL with a value specifying the indirect I/O register to be accessed. Software
then reads or writes the IOWIN for the desired data from/to the I/O register specified
by the index from the IOREGSEL. Software must access the IOWIN register as a dword
quantity.
Notes:
• SW can only write to bits 1,2,3,5 and 6 of the IOREGSEL registers. Bits 0 and
4 are reserved. Example : if SW wants to access the IOWIN for index 15
{5’b01111}, then the IOREGSEL register must be programmed with value
{6’b01_111_}