Datasheet

Processor Core
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
100 Document Number: 333577-002EN
11.4.1.6 IRR
This register contains the active interrupt requests that have been accepted, but
not yet dispatched to the core for servicing. When the MVIC accepts an interrupt, it
sets the bit in the IRR that corresponds to the vector of the accepted interrupt.
When the core is ready to handle the next interrupt, it will sent an INTA cycle and
the MVIC clears the highest priority IRR (Interrupt Request Register) bit that is set
and sets the corresponding ISR bit. Note that if the interrupt line for the IRR is not
cleared, then the IRR bit will NOT be cleared when the INTA is sent by the CPU.
31
0
3233
63 62
30
1
11.4.1.7 LVTTIMER
• Is used to inject an interrupt when the timer inside the MVIC expires.
• In the current implementation, lines 0 to 15 can be used to inject timer interrupts
to the CPU.
• SW can programs bits 3-0 of the LVTTIMER register to indicate which interrupt line
needs to be converted into a timer interrupt. Based on the line programmed, when
the timer expires, the MVIC will inject the corresponding vector (0x20 to 0x2f). This
interrupt line must be configured for edge mode.
• Bit 16 is the mask bit
• Bit 17 is the periodic mode bit.
31
0
Line Number
MP
16 3
0 0 01
4567815
Reserved
1718
0