Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
10 Document Number: 333577-002EN
16.3.1.45 Clear for IntErr Interrupt (CLEAR_ERR) ...................... 326
16.3.1.46 Combined Interrupt Status (STATUS_INT) .................. 327
16.3.1.47 Source Software Transaction Request (REQ_SRC_REG) 328
16.3.1.48 Destination Software Transaction Request register
(REQ_DST_REG) .................................................... 328
16.3.1.49 Source Single Transaction Request
(SGL_REQ_SRC_REG) ............................................. 329
16.3.1.50 Destination Single Software Transaction Request
(SGL_REQ_DST_REG) ............................................. 330
16.3.1.51 Source Last Transaction Request (LST_SRC_REG) ....... 331
16.3.1.52 Destination Single Transaction Request
(LST_DST_REG) ..................................................... 331
16.3.1.53 DMA Configuration (DMA_CFG_REG) ......................... 332
16.3.1.54 Channel Enable (CH_EN_REG) .................................. 332
16.3.1.55 DMA ID (DMA_ID_REG) ........................................... 333
16.3.1.56 DMA Test (DMA_TEST_REG) ..................................... 334
16.3.1.57 DMA Component ID - LOWER (DMA_COMP_ID_L) ........ 334
16.3.1.58 DMA Component ID - UPPER (DMA_COMP_ID_U) ........ 335
17 General Purpose I/O (GPIO) ........................................................................... 336
17.1 Signal Descriptions ............................................................................. 336
17.2 Features ........................................................................................... 336
17.3 Memory Mapped IO Registers ............................................................... 336
17.3.1.1 Port A Data (GPIO_SWPORTA_DR) ............................ 337
17.3.1.2 Port A Data Direction (GPIO_SWPORTA_DDR) ............. 338
17.3.1.3 Port A Data Source (GPIO_SWPORTA_CTL)................. 339
17.3.1.4 Interrupt Enable (GPIO_INTEN) ................................ 339
17.3.1.5 Interrupt Mask (GPIO_INTMASK) .............................. 340
17.3.1.6 Interrupt Type (GPIO_INTTYPE_LEVEL) ...................... 341
17.3.1.7 Interrupt Polarity (GPIO_INT_POLARITY) .................... 342
17.3.1.8 Interrupt Status (GPIO_INTSTATUS) ......................... 342
17.3.1.9 Raw Interrupt Status (GPIO_RAW_INTSTATUS) .......... 343
17.3.1.10 Debounce Enable (GPIO_DEBOUNCE) ........................ 343
17.3.1.11 Clear Interrupt (GPIO_PORTA_EOI) ........................... 344
17.3.1.12 Port A External Port (GPIO_EXT_PORTA) .................... 345
17.3.1.13 Synchronization Level (GPIO_LS_SYNC) ..................... 345
17.3.1.14 Interrupt both edge type (GPIO_INT_BOTHEDGE) ....... 346
17.3.1.15 GPIO Configuration Register 2 (GPIO_CONFIG_REG2) .. 347
17.3.1.16 GPIO Configuration Register 1 (GPIO_CONFIG_REG1) .. 347
18 Timers and PWM ........................................................................................... 348
18.1 Signal Descriptions ............................................................................. 348
18.2 Features ........................................................................................... 348
18.2.1 PMW Signaling ...................................................................... 349
18.2.2 Functional Operation .............................................................. 349
18.3 Use .................................................................................................. 350
18.3.1 PWM Mode ........................................................................... 350
18.3.2 Timer Mode .......................................................................... 351
18.4 Memory Mapped IO Registers ............................................................... 351
18.4.1.1 Timer 1 Load Count (Timer1LoadCount) ..................... 352
18.4.1.2 Timer 1 Current Value (Timer1CurrentValue) .............. 352
18.4.1.3 Timer 1 Control (Timer1ControlReg) .......................... 353
18.4.1.4 Timer 1 End Of Interrupt (Timer1EOI) ....................... 355
18.4.1.5 Timer 1 Interrupt Status (Timer1IntStatus) ................ 355