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Document Number: 333577-002EN

Intel

Quark™ microcontroller

D2000

Datasheet

January 2016

Summary of content (475 pages)

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Intel® Quark™ microcontroller D2000 Datasheet January 2016 Document Number: 333577-002EN
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Introduction You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice.
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Introduction Contents 1 Introduction .................................................................................................. 16 1.1 2 Pin States Through Reset ..................................................................... 21 External Interface Signals ..................................................................... 21 GPIO Multiplexing ................................................................................ 26 Ballout and Package Information ..............................
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Introduction 4.6.3 4.6.4 4.6.5 5 Register Access Methods ................................................................................. 51 5.1 5.2 6 6.2 Signal Descriptions .............................................................................. 57 Features ............................................................................................ 57 7.2.1 System Clock - Hybrid Oscillator ............................................... 58 7.2.2 RTC Oscillator .................................
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Introduction 9.3 10 Thermal Management ..................................................................................... 87 10.1 11 Overview ........................................................................................... 87 Processor Core .............................................................................................. 88 11.1 11.2 11.3 11.4 11.5 12 Reset Behavior.................................................................................... 83 9.3.
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Introduction 12.4.3 12.4.4 13 12.4.2.6 FLASH_STTS (FLASH_STTS) ..................................... 125 12.4.2.7 CTRL (CTRL) .......................................................... 126 12.4.2.8 FPR0_RD_CFG (FPR0_RD_CFG) ................................ 127 12.4.2.9 FPR1_RD_CFG (FPR1_RD_CFG) ................................ 128 12.4.2.10 FPR2_RD_CFG (FPR2_RD_CFG) ................................ 129 12.4.2.11 FPR3_RD_CFG (FPR3_RD_CFG) ................................ 130 12.4.2.
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Introduction 13.3.1.28 13.3.1.29 13.3.1.30 13.3.1.31 13.3.1.32 13.3.1.33 13.3.1.34 13.3.1.35 13.3.1.36 13.3.1.37 13.3.1.38 13.3.1.39 13.3.1.40 13.3.1.41 13.3.1.42 Enable (IC_ENABLE) ............................................... 175 Status (IC_STATUS) ................................................ 177 Transmit FIFO Level (IC_TXFLR) ............................... 179 Receive FIFO Level (IC_RXFLR)................................. 179 SDA Hold (IC_SDA_HOLD) .......................................
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Introduction 15.3.1.5 15.3.1.6 15.3.1.7 15.3.1.8 15.3.1.9 15.3.1.10 15.3.1.11 15.3.1.12 15.3.1.13 15.3.1.14 15.3.1.15 15.3.1.16 15.3.1.17 15.3.1.18 15.3.1.19 15.3.1.20 15.3.1.21 15.3.1.22 15.3.1.23 15.3.1.24 15.3.1.25 15.3.1.26 15.3.1.27 15.3.1.28 15.3.1.29 15.3.1.30 15.3.1.31 15.3.1.32 15.3.1.33 15.3.1.34 15.3.1.35 15.3.1.36 15.3.1.37 15.3.1.38 15.3.1.39 15.3.1.40 15.3.1.41 15.3.1.42 15.3.1.43 15.3.1.44 15.3.1.45 15.3.1.46 15.3.1.47 15.3.1.48 15.3.1.49 15.3.1.50 15.3.1.51 15.3.1.52 15.3.1.53 15.3.1.54 15.
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Introduction 15.3.1.57 15.3.1.58 15.3.1.59 15.3.1.60 15.3.1.61 16 Data Register (DR32) .............................................. 273 Data Register (DR33) .............................................. 274 Data Register (DR34) .............................................. 275 Data Register (DR35) .............................................. 275 RX Sample Delay Register (RX_SAMPLE_DLY) ............. 276 DMA Controller .................................................................................
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Introduction 16.3.1.45 16.3.1.46 16.3.1.47 16.3.1.48 16.3.1.49 16.3.1.50 16.3.1.51 16.3.1.52 16.3.1.53 16.3.1.54 16.3.1.55 16.3.1.56 16.3.1.57 16.3.1.58 17 General Purpose I/O (GPIO) ........................................................................... 336 17.1 17.2 17.3 18 Signal Descriptions ............................................................................. 336 Features ...........................................................................................
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Introduction 18.4.1.6 18.4.1.7 18.4.1.8 18.4.1.9 18.4.1.10 18.4.1.11 18.4.1.12 18.4.1.13 Timer 2 Load Count (Timer2LoadCount) ..................... 356 Timer 2 Current Value (Timer2CurrentValue) .............. 356 Timer 2 Control (Timer2ControlReg) .......................... 357 Timer 2 End Of Interrupt (Timer2EOI) ....................... 357 Timer 2 Interrupt Status (Timer2IntStatus) ................ 358 Timers Interrupt Status (TimersIntStatus) ..................
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Introduction 21.1 21.2 21.3 22 Analog to Digital Convertor (ADC) ................................................................... 383 22.1 22.2 22.3 22.4 23 Signal Descriptions ............................................................................. 383 Features ...........................................................................................383 Use ..................................................................................................384 Memory Mapped IO Registers .........
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Introduction 24.3.1.24 24.3.1.25 24.3.1.26 24.3.1.27 24.3.1.28 24.3.1.29 24.3.1.30 24.3.1.31 24.3.1.32 24.3.1.33 24.3.1.34 24.3.1.35 24.3.1.36 24.3.1.37 24.3.1.38 24.3.1.39 24.3.1.40 24.3.1.41 24.3.1.42 24.3.1.43 24.3.1.44 24.3.1.45 24.3.1.46 24.3.1.47 24.3.1.48 24.3.1.49 24.3.1.50 24.3.1.51 24.3.1.52 24.3.1.53 24.3.1.54 24.3.1.55 24.3.1.56 24.3.1.57 January 2016 Document Number: 333577-002EN General Purpose Scratchpad Register 3 (GP3) ............. 427 Write-Once Scratchpad Register (WO_SP) ............
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Introduction 24.3.1.58 24.3.1.59 24.3.1.60 24.3.1.61 24.3.1.62 24.3.1.63 24.3.1.64 24.3.1.65 24.3.1.66 24.3.1.67 24.3.1.68 24.3.1.69 24.3.1.70 24.3.1.71 24.3.1.72 24.3.1.73 24.3.1.74 24.3.1.75 24.3.1.76 24.3.1.77 24.3.1.78 24.3.1.79 24.3.1.80 25 AON Counters ..............................................................................................474 25.1 Features ...........................................................................................474 25.1.1 AON Counter ........................
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Introduction Revision History Date Revision Description Jan 2016 002 Initial public release Dec 2015 001 Internal release available by NDA § January 2016 Document Number: 333577-002EN Intel® Quark™ microcontroller D2000 Datasheet 15
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Introduction 1 Introduction The Intel® Quark™ microcontroller D2000 is an ultra-low power Intel Architecture (IA) SoC that integrates an Intel® Quark processor core, Memory Subsystem with ondie volatile and non-volatile storage, and I/O interfaces into a single low-cost systemon-chip solution. Figure 1 shows the system level block diagram of the SoC. Refer to the subsequent chapters for detailed information on the individual functional blocks. Figure 1.
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Introduction 1.1 Feature Overview 1.1.1 Clock Oscillators • • 1.1.2 Quark Processor Core • • • • • 1.1.3 • • • • • 32 KB of 64b wide on-die Flash Supports Page Erase and Program cycles Supports configurable wait states to allow Flash to run at various frequencies.
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Introduction • • • • 1.1.6 SPI • • • • • • 1.1.7 • • • • • Provides 25 independently configurable GPIO All GPIOs are interrupt capable supporting level sensitive and edge triggered modes Debounce logic for interrupt source All 25 GPIOs are Always-on interrupt and wake capable Timers • • • 1.1.
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Introduction 1.1.11 Watchdog Timer • 1.1.12 Real Time Clock (RTC) • • • 1.1.13 • • • • • 19 Analog Input channels Selectable 6/8/10/12-bit resolution Supports maximum of 2.28 Mega Samples Per Second (MSps) at 12-bit resolution and 4 MSps at 6-bit resolution) Differential Non-Linearity DNL of +/- 1.0 LSB Integral Non-Linearity INL of +/- 2.0 LSB SINAD of 68 dBFS Offset Error of +/- 2 LSB (calibration enabled), +/- 64 LSB (calibration disabled) Full-scale input range of 0 to AVDD.
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Introduction 1.1.16 Power Management • • • SoC System States : RUN, Low Power Compute, HALT, Low Power Wait, Deep Sleep (RTC or NORTC) state. Processor States : C0 – C2 Supports Coin-cell Battery source (2.0V to 3.6V range) Scenario 1.1.
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Physical Interfaces 2 Physical Interfaces 2.1 Pin States Through Reset All functional IOs will come up in input mode after reset except JTAG TDO output which is kept tristated. All Digital IO include a configurable pullup (49K ohm typ; 34K-74Kohm range) with pull-up disabled by default, except for F_20, F_22, F_23 pins (TRST_N, TMS, TDI)) where pull-up is enabled by default. The state of all IOs is retained whenever SoC goes into low power states. 2.
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Physical Interfaces Interface Clocking Pin Name IOVDD Supply VSENSE Analog input GSENSE LX VREN Analog input Supply Analog input DVDD Supply DVDD_2 Supply HYB_XTALI Logic input HYB_XTALO Logic output RTC_XTALI Logic input Intel® Quark™ microcontroller D2000 Datasheet 22 Type Description Analog (Driver) side Voltage Rail Input for IO ring (1.8V to 3.3V Nominal +/- 10%). All digital IO pads use IOVDD only. IOVDD can be an AC isolated version of PVDD but is not required.
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Physical Interfaces Interface Reset GPIO I2C PWM UART Pin Name Type Description RTC_XTALO Logic output SYS_CLK_OUT Logic Output RTC_CLK_OUT RST_N Logic Output Analog input GPIO[24:0] I2C_SCL I2C_SDA PWM1 PWM0 UART_A_TXD Logic I/O Logic I/O Logic I/O Logic Output Logic Output Logic output UART_A_RXD Logic input UART_A_RTS Logic output UART_A_CTS UART_A_DE Logic input Logic Output Crystal output for RTC clock. If RTC XTAL is not connected, this pin has to be grounded (to 0).
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Physical Interfaces Interface Slave SPI Master SPI Pin Name UART_A_RE Logic Output UART_B_TXD Logic output UART_B_RXD Logic input UART_B_RTS Logic output UART_B_CTS UART_B_DE Logic input Logic Output UART_B_RE Logic Output SPI_S_SCLK SPI_S_SDIN SPI_S_SCS SPI_S_SDOUT SPI_M_SCLK SPI_M_TXD SPI_M_SS[3:0] SPI_M_RXD Logic input Logic input Logic input Logic output Logic output Logic output Logic output Logic input Intel® Quark™ microcontroller D2000 Datasheet 24 Type Description depending o
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Physical Interfaces Interface Analog JTAG Pin Name Type Description AI[18:0] Analog input AR Analog input TRST_N Logic input TDI Logic input TMS Logic input TCK TDO Logic input Logic output Comparator/ADC inputs. AI[18:0] are connected to both ADC and comparator inputs. AI[5:0] are connected to 6 fast response analog comparators.
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Physical Interfaces 2.3 GPIO Multiplexing Not all interfaces can be active at the same time. To provide flexibility, these shared interfaces are multiplexed with GPIOs. Note: All 25 functional IOs come up as Function 0 at boot. JTAG is default enabled (as part of Function 0) instead of GPIO[23:19]. FW is responsible for enabling proper configuration later on. Table 2.
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Ballout and Package Information 3 Ballout and Package Information The Intel® Quark™ microcontroller D2000 comes in 6 mm x 6 mm Quad Flat No-Leads (QFN) Package. 3.1 SoC Attributes • • Package parameters: 6 mm X 6 mm (QFN) Ball Count: 40 All Units: mm • • Tolerances if not specified: .X: ± 0.1 .XX: ± 0.05 • Angles: ± 1.
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Ballout and Package Information 3.2 Package Diagrams Figure 2. Package Diagram QFN 40 pin (0.
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Ballout and Package Information Figure 3.
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Ballout and Package Information 3.3 Pin Multiplexing There are 15 dedicated pins + 1 QFN GND plane and 25 functional pins which can be configured as GPIO (GPIO[24:0]) or other functions (I2C/UART/SPI/JTAG). There are two major IO modes: user mode and test mode. In user mode, each pin can be individually configured in one of the 4 user modes (FUNC 0/1/2/3). By default, after power-on-reset (RST_N) or cold reset, SoC comes up in user mode 0 function (FUNC0).
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Ballout and Package Information Pin Num ber Pin/Ball Name Type Volta ge 35 F_4 GPIO 36 F_5 GPIO 37 F_6 GPIO 38 F_7 GPIO 39 F_8 GPIO 11 F_9 GPIO 2 F_10 GPIO 3 F_11 GPIO 4 F_12 GPIO 5 F_13 GPIO IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD 6 F_14 GPIO IOVDD/ AVDD 7 F_15 GPIO 8 F_16 GPIO 9 F_17 GPIO 10 F_18 GPIO IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD IOVDD/ AVDD 18 F_19 GPIO 13 F_20
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Ballout and Package Information All Digital IO include configurable drive strength namely low-drive (12 mA) and highdrive (16 mA) modes. By default, all digital IOs come up in low-drive mode. All Digital IO include a configurable pullup with pull-up disabled by default, except for F_20, F_22, F_23 (TRST_N, TMS, TDI)) where pull-up is enabled by default. UART_A/B_CTS (input) or UART_A/B_RE (output) is available based on UART mode of operation (RS232 or RS485) configurable in respective UART controller.
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Ballout and Package Information 3.4 Alphabetical Ball Listing Table 4 shows pins arranged in increasing order of pin number. Table 4.
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Ballout and Package Information Pin Numbe r Pin/Ball Name Typ e Voltage 18 F_19 GPIO IOVDD 19 HYB_XTALI CLK DVDD 20 HYB_XTAL O CLK DVDD 21 F_24 GPIO IOVDD 22 RTC_XTALI CLK DVDD 23 RTC_XTAL O CLK DVDD 24 DVDD_2 PWR 25 GSENSE 26 Function 0 Function 1 Function 2 TDO GPIO19 HYB_XTALI HYB_XTALI HYB_XTAL O HYB_XTAL O GPIO24 - RTC_XTALI RTC_XTALI RTC_XTAL O RTC_XTAL O DVDD_2 DVDD_2 DVDD_2 DVDD_2 DVDD_2 PWR 0V GSENSE GSENSE GSENSE GSENSE LX PWR DVDD LX
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Ballout and Package Information Pin Numbe r Pin/Ball Name Typ e Voltage Function 0 Function 1 Function 2 Function 3 38 F_7 GPIO IOVDD/AVD D GPIO7 AI7 I2C_SDA 39 F_8 GPIO IOVDD/AVD D GPIO8 AI8 SPI_S_SCLK 40 AVDD PWR PVDD AVDD AVDD AVDD AVDD VSS GND PWR 0V GND GND GND GND 3.5 Platform Requirements 3.5.1 3.5.1 Internal Voltage Regulator Figure 4. Supply Rail 2.0V – 3.6V Internal Voltage Regulator Cin L PVDD VREN AVD LX EN Cout LX VSENSE VREG 1.
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Ballout and Package Information The requirement for external component at PCB level is as shown in the table: Component Name Description Characteristic Value Accuracy Unit Cin Input Capacitor Ceramic 470 +/- 20% nF Cout Output Tank Capacitor Ceramic 4.
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Ballout and Package Information Item GNDSENSE AVS VDD_CTRL DVDD LX VOUT CIN Description Maximum total resistance (including wirebond, package pin and board routing) between GNDSENSE and Ground plane must be less than 400mΩ. This pin should be star connected to the reference (GND) of the load circuit. No load current should flow through this connection. Maximum total resistance (including wirebond, package pin and board routing) between AVS and Ground plane must be less than 400mΩ/nb AVS pads.
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Ballout and Package Information 3.5.3 Hybrid Oscillator Hybrid oscillator can work in internal Silicon RC oscillator mode with +/- 2% accuracy (after trimming). If a system does not require higher accuracy system clock, then HYBOSC 32MHz XTAL need not be mounted on board to save cost and in such case, keep HYB_XTAL1, HYB_XTAL0 pins as no-connect (floating). A programmable capacitive load can be added on the crystal terminals internal to the chip to fine tune the crystal frequency.
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Ballout and Package Information 3.5.4 ADC A simple filter is recommended to be put on board on Analog Inputs [19:0] connected to ADC, to reduce external noise. It should be understood that any additional frequency signals within the band of interest will be present in the output spectrum contributing for a performance impact. Additionally the input signal is disturbed by the fast transients due to the fast charging of the ADC input capacitor during the start of the sampling period.
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Electrical Characteristics 4 Electrical Characteristics 4.1 Thermal Specifications Ambient temperature = -40°c to +85°c. 4.2 Voltage and Current Specifications 4.2.1 Absolute Maximum Ratings Table 6: Absolute Maximum Voltage Ratings Symbol PVDD Ratings Battery Supply min 2.0 Max 3.63 Unit V Notes • • • AVDD IOVDD Analog Supply Digital IO Supply 2.0 3.63 V • • 1.62 3.63 V • • • • • DVDD/DVDD_2 Regulated Core Voltage Intel® Quark™ microcontroller D2000 Datasheet 40 1.62 1.
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Electrical Characteristics Symbol Ratings min Max Unit Notes • DVDD/DVDD_2 Retention mode 1.35V during Deep Sleep Power State 1.2 1.43 • V Connected to external VR (if VREN=0); or to Internal VR output (if VREN=1)(post LC circuit on LX output pin; see HAS Chap08). If external voltage regulator, current draw is 50 mA max. In Deep Sleep Power State, there is an option to lower core voltage to 1.
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Electrical Characteristics Symbol Co CL Ftol Dlev Output clock frequency accuracy over PVT Startup time Parameter Min Crystal Shunt Cap Crystal Load Cap Frequency Tolerance Drive Level (25Ω) Without crystal (si osc mode) after trim done at typical temperature With crystal before trim (excluding crystal frequency tolerance) 0.84 With crystal after trim Si osc mode – frequency setting within 2% accuracy Crystal mode – frequency settling within 100ppm accuracy Typ Max Unit 1.
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Electrical Characteristics Symbol Parameter CL Crystal Load Cap Ftol Frequency Tolerance Dlev Drive Level 4.4 DC Specifications 4.4.1 IO DC specifications Min Typ Max 7 Unit pF -20 20 ppm 1 µW For IOVDD=3.3V: Symbol Parameter Min Typ Max Unit VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2 3.6 V VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 IOL 12mA @ VOL 14.1 22.9 31.8 mA 16mA @ VOL 18.8 30.6 42.4 mA 12mA @ VOH 20.7 41.9 69.
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Electrical Characteristics Symbol VT- Parameter Schmitt Trigger H-> L Threshold Point Min 1.13 Typ 1.2 Max 1.27 Unit V FOR IOVDD=1.8V: Symbol Parameter Typ Max Unit VIL Input Low Voltage -0.3 0.63 V VIH Input High Voltage 1.17 3.6 V VOL Output Low Voltage 0.45 V VOH Output High Voltage 1.35 IOL 12mA @ VOL 5.8 12.1 21.6 mA 16mA @ VOL 7.7 16.2 28.7 mA 12mA @ VOH 4.7 12.0 24.3 mA 16mA @ VOH 6.6 16.7 33.
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Electrical Characteristics 4.4.2 Undershoot Voltage Support SoC supports a undershoot voltage of 300 mV (VIL min of -0.3V) on its input pins. 4.4.3 ADC IO DC characteristics Symbol Parameter Full-scale input range Min Typ 0 Max Unit 3.63 V VREFP Positive reference voltage 2 AVDD AVDD V AGNDREF Negative reference voltage 0 0 0.
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Electrical Characteristics 4.5 System Power Consumption The data is preliminary and subject to revision in future. Scenario Condition Total Active Power (Pavdd + Ppvdd + Piovdd) with Internal VR enabled. - CPU running Coremark benchmark workload - All peripherals clock gated - Hybrid Oscillator and RTC Oscillator running - ADC and Comparators powered down Vpvdd=Vavdd=Viovdd=3.3V Min Typ - 26.4 Max Unit mW fCPU = 32 MHz, -40≤T≤850c Vpvdd=Vavdd=Viovdd=3.3V 16.
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Electrical Characteristics Scenario Condition Total Deep Sleep RTC Current (Ipvdd + Iavdd + Iiovdd) with AON Periodic Timer Wake. - CPU in C2 power state (executed HALT instruction) - All peripherals clock gated - Hybrid Oscillator powered down and RTC Oscillator running - ADC and Comparators powered down - Internal Voltage Regulator enabled in Linear Regulator mode (1.8V or 1.35V voltage output) Vpvdd=Vavdd=Viovdd=3.
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Electrical Characteristics Scenario - CPU in C2 power state (executed HALT instruction) - All peripherals clock gated - Hybrid Oscillator and RTC Oscillator powered down - ADC and Comparators powered down. - 1 GPIO input enabled for level sensitive interrupt wake - Internal Voltage Regulator enabled in Linear Regulator mode (1.8V or 1.35V voltage output) Condition Vpvdd=Vavdd=Viovdd=3.3V Min Typ - 1.3 Max Unit µA Vdvdd = 1.35V, -40≤T≤850c 4.6 AC Specifications 4.6.
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Electrical Characteristics Parameter Min Hold time of SPI_M_RXD with respect to SPI_M_SCLK sampling edge Max 0 ns - Output load supported for SPI_M_TXD, SPI_M_SS[3:0], SPI_M_SCLK outputs is 25 pF max to support max rate of 16 Mbps. 4.6.2 SPI Slave IO AC characteristics SPI Slave interface consists of: • Outputs SPI_S_SDOUT • Inputs SPI_S_SCLK, SPI_S_SDIN, SPI_S_SCS As per SPI protocol, the interface is timed with respect to SPI_S_SCLK which is input to SoC.
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Electrical Characteristics 4.6.4 General IO AC characteristics Output load supported for all other IO outputs such as GPIO outputs, PWM, UART is 50 pF max and 5 pF min. UART interface supports maximum baud rate of 2 Mbaud when system clock frequency is 32 MHz. All GPIO and PWM outputs will get reflected within 1 system clock period of 30ns on the output pins. 4.6.5 JTAG Interface AC characteristics The JTAG interface is a 5-pin interface timed with respect to TCK input clock.
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Register Access Methods 5 Register Access Methods All SoC registers are accessed as Fixed Memory Mapped Registers. The SoC does not contain any of these traditional x86 memory register types: Fixed IO, IO Referenced, Memory Referenced, PCI Configuration or Message Bus Registers. 5.1 Fixed Memory Mapped Register Access Fixed Memory Mapped IO (MMIO) registers are accessed by specifying their 32-bit address in a memory transaction from the CPU core. This allows direct manipulation of the registers.
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Register Access Methods Access Type Meaning Description Default Default When the processor is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration.
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Mapping Address Spaces 6 Mapping Address Spaces The SoC supports a single flat Memory address space. The SoC does not support IO Address Space, PCI Configuration Space or Message Bus Space. The Lakemont Processor core (LMT) can directly access memory space either through code fetches over ITCM or data fetches over DTCM or through memory reads and writes over AHB fabric. This chapter describes how memory space is mapped to interfaces and peripherals in the SoC. 6.
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Mapping Address Spaces Table 10 SoC Memory Map Function Start Address End Address Size LAPIC 0xFEE0_0000 0xFEE0_0FFF 4KB IOAPIC 0xFEC0_0000 0xFECF_FFFF 1MB SCSS (System Control Subsystem) 0xB080_0000 0xB080_3FFF 16KB DMA 0xB070_0000 0xB070_0FFF 4KB Internal SRAM Configuration 0xB040_0000 0xB040_03FF 1KB Flash Configuration 0xB010_0000 0xB010_03FF 1KB ADC 0xB000_4000 0xB000_43FF 1KB I2C_0 0xB000_2800 0xB000_2BFF 1KB UART_B 0xB000_2400 0xB000_27FF 1KB UART_A 0xB000_20
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Mapping Address Spaces LMT clock is gated by HW autonomously based on HALT detection. It is ungated by HW upon Interrupt assertion. There is an option to gate/ungate clock to Memory subsystem too with LMT clock. Other than LMT and Memory subsystem clocks, for all other functions, SW controls gate/ungate of their respective clocks. 6.2 SoC Fabric The SoC Fabric is a multi-layer AHB fabric that provides interconnect between 2 Masters and 5 Slaves.
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Mapping Address Spaces Table 11 Multi-Layer AHB Fabric Master ID List AHB Master ID Codes AHB Master ID Code LMT 0x1 DMA 0x4 APB Fabric has 10 slaves – GPIO, I2C Master/Slave, SPI Master, SPI Slave, 2 UARTs, ADC, RTC, WDT and Timers block. Even though DMA engine can perform concurrent transfers, single outstanding transaction limitation of AHB prevents simultaneous transfers to/from multiple peripherals.
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Clocking 7 Clocking The Intel® Quark™ microcontroller D2000 clocking is controlled by the Clock Control Unit (CCU). There are 2 primary clocks in Intel® Quark™ microcontroller D2000, a System clock and an RTC clock. The sources and frequencies of the primary clocks are described in subsequent sections. The CCU uses the primary clocks to generate secondary clocks to sub modules in the SoC. The secondary clocks are gated and scaled versions of the primary clocks. 7.
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Clocking - In “Low Power Compute” state of SoC, hybrid oscillator can be scaled down to 4 MHz with prescaler of 32 to get 125 kHz; or 32.768kHz (RTC clock wherein hybrid oscillator can be powered down). In a minimalistic system configuration that does not require RTC clock or strict clock accuracy (< 100ppm) of system clock, such platforms can choose not to mount 32.768kHz XTAL and/or not to mount 32MHz XTAL and choose to work with 32MHz Silicon RC oscillator mode of hybrid oscillator.
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Clocking • • Bypass mode allows an external clock (fed through RTC_XTALI pin) to be provided through the RTC oscillator. To achieve this, OSC1_BYP_XTAL_UP=1 and OSC1_PD=0) 600mS start-up time to reach +/-20ppm The Intel® Quark™ microcontroller D2000 is designed to operate without RTC clock as well, if platform does not require RTC clock. RTC clock is needed for any of the following reasons: • • • Periodic waking in low power sleep state.
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Clocking 7.2.4.2 Flash DFS requirements When using DFS on the root fabric clock the flash wait states must be adjusted for both Flash instances. Refer to Memory Subsystem chapter for further details. 7.2.5 Dynamic Clock Gating The Intel® Quark™ microcontroller D2000 supports a wide range of clock gating options 1) Each leaf clock can be dynamically gated by firmware To apply a DCG the following procedure should be used.
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Power Management 8 Power Management This chapter provides information on the power management and power architecture of the SoC. Power architecture of SoC is based on the following premise: 1. 2. 3. There is no requirement to supply regulated voltage (1.8v or 3.3v) to platform components from SoC. a. This dictates the max current specification of internal voltage regulator in the SoC. Platform Components and SoC would operate from same battery source (eg coincell). a.
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Power Management 8.1 Component Power States 8.1.1 Voltage Regulator Table 13. VR Power States Power State Definition Max Current Entry Latency Exit Latency How Triggered NRML-1.8V Normal mode. Voltage regulator (Retention Alternating Regulator) functions in switching regulator (eSR) mode and able to output 50 mA current. eSR output regulates. iLR-RET output set to high impedance. EN=H, VREGSEL=L. Change in power state incurs tSTRB of 1 usec + tROK_PROG (TBD).
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Power Management “OFF” power state is entered only when internal regulator is disabled using VREN=L input pin and 1.8v rail (DVDD input) is fed directly from platform. Voltage regulator in eSR mode has 90% efficiency down to 0.2 Imax (1 mA) and 70% efficiency down to 0.01 Imax (500 uA). In iLR mode, power consumption of VR is about 1% of delivered current. The SoC power delivery is described in detail in the Power Architecture section. 8.1.2 CPU Table 14.
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Power Management 8.1.3 ADC Table 15. ADC Power States Power State Definition Entry Latency Exit Latency How Triggered ON Normal Operation. ADC is enabled for conversation with optionally enabled internal LDO. Enadc=H, enldo=H, dislvl=L. powerup time: 3-5-10 usec (min-typ-max). 1000 uA @ avdd, 100 uA @ dvdd at 5 MSps - - Writing to ADC_OP_MODE register STBY Standby Mode. ADC is disabled but ADC state is kept enabled by enabling internal LDO and retaining DVDD. Enadc=L, enldo=H, dislvl=L.
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Power Management 8.1.4 Comparator Table 16. Comparator (CMP) Power States Power State ON Definition Normal operation. CMP_PWR=H. Max Current Entry Latency Exit Latency How Triggered Fast: - - Writing to CMP_PWR register - 0.9 us Writing to CMP_PWR register How Triggered 20.5 uA @ avdd, 0.82 uA @ dvdd. Slow: 2.5 uA @ avdd, 1.4 uA @ dvdd. OFF 8.1.5 Powered down state. CMP_PWR=L. 2.7 nA 32.768 kHz OSC Table 17. 32.
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Power Management 8.1.6 32 MHz OSC Table 18. 32 MHz OSC Power States Power State 8.1.7 Definition Max Current Entry Latency Exit Latency How Triggered ON-SI Silicon RC Oscillator mode. Oscillator is outputting the configured clock frequency at +/- 2% accuracy. 450 uA @ 32 MHz; 180 uA @4 MHz. 2 usec - Writing to OSC0_CFG0/1 register ON-XTAL Crystal Oscillator mode. Oscillator is outputting the configured clock frequency (based on crystal connected) at +/- 100 ppm accuracy.
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Power Management Power State STBY Definition Power Reduction mode (stand-by). this mode corresponds to a memory that cannot perform any read (or write) operation. This mode is activated by a CSN at high level at the rising edge of CK. Max Current Entry Latency Exit Latency How Triggered - 0 0 Chip Select CSN=H to SRAM deasserted in a clock cycle for write or read operation There is no specific control to put the SRAM into above power states.
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Power Management 8.2 System Power States 8.2.1 System Power State Diagram Figure 6.
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Power Management 8.2.2 System Power State Definition The Power Management states supported by the SoC are described in this section. Table 21. SoC Power States State ACTIVE HALT Sub State Description RUN Main supply rail is present and voltage regulator is in regulation in Normal mode. System clock is running from 4MHz up to 32MHz. Processor in C0. FW has full control of which peripherals to enable.
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Power Management 8.2.3 Power and Latency Requirements The System power states are maintained and managed in FW. Table 22. Power and Latency Requirements SoC Power State Max Current TYP TYP 25C 105 Latency Entry Exit Component Power State CPU VR ADC CM SRAM P C <10 RUN - mA 32 32.76 Bus IO MH 8 kHz Cloc Stat k e z <5 <2 usec usec C0 NRML Any Any NRML ON ON ON ON ON/ ON <4 ON / STBY LOW POWER COMPUT E <1. HALT <4 5. 6. 7.
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Power Management 8.2.4 Minimum Voltage Limits (Vmin) Table 23. Minimum Voltage Limits Component Condition PVDD/IOVDD/ AVDD Min Max DVDD Min Max RAR Voltage Regulator Normal operation 1.62 V 3.63 V 1.08 V 3.63 V ADC Normal or Power Down 1.62 V 3.6 V 1.62 V 1.98 V Comparator Normal or Power Down 2.0 V 3.63 V 1.2 V 1.98 V SRAM Normal operation - - 1.2 V 1.98 V Flash Normal operation - - 1.2 V 1.98 V Digital IO pads Normal operation - - 1.62 V 1.
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Power Management 8.3 Power Architecture Figure 7. Intel® Quark™ microcontroller D2000 Power Architecture PLATFORM Supply Rail 2.0V – 3.6V 470nF 47uH PVDD VREN AVD LX EN 4.7uF LX VSENSE VSENSE RAR 1.
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Power Management The Intel® Quark™ microcontroller D2000 power architecture is given in Figure 6 and uses a Retention Alternating Regulator (RAR). RAR works in two modes – normal mode wherein Switching Regulator is turned on sourcing 50 mA of max current and retention mode wherein linear regulator is turned on sourcing only 300 uA of max current. The entire SoC core is under single power domain (1.8v regulated output rail from RAR) and is never power gated.
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Power Management 8.4 Power Management Unit (PMU) 8.4.1 Internal Voltage Regulator Internal voltage regulator is enabled by pulling high VREN to PVDD. 1. 2. 3. 4. 5. 6. PVDD/AVDD/IOVDD are applied together. All these rails are from same source. After 240 usec of start-up time, Voltage regulator achieves regulated 1.8V DVDD in switching voltage regulator mode. a.
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Power Management 8.4.2 External Voltage Regulator Internal voltage regulator is disabled by grounding VREN to GND. In this case, DVDD voltage input is supplied by an external voltage regulator. Here DVDD has to be applied before IOVDD. 1. 2. 3. 4. 5. 6. 7. PVDD/AVDD/DVDD are applied together. Wait for DVDD rail to ramp-up to stable regulated value. As DVDD is stable, Hybrid oscillator starts oscillating in Silicon RC oscillator mode outputting 4MHz +/- 40% (trimcode is not applied at this stage).
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Power Up and Reset Sequence 9 Power Up and Reset Sequence This chapter provides information on the following topics: • Power Up Sequences • Power Down Sequences • Reset Behavior 9.1 Power Up Sequences There are two cases of power up: a. b. RST_N triggered Power Up (Any state to ACTIVE state). Covers Power recycling. From any Low Power State to ACTIVE state (based on any of configured wake events) Hardware (PMU) supports enabling on-die RAR Voltage Regulator.
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Power Up and Reset Sequence 4. 5. 6. 7. 9.1.2 PMU generates a strobe on VSEL_STROBE to RAR to put it in eSR mode at 1.8V VSEL_IN. Pulse width of VSEL_STROBE is based on PM_WAIT.VSTRB_WAIT register. At the positive edge of VSEL_STROBE, RAR deasserts ROK_BUF_VREG (if it is enabled/selected by VR_EN input). a. When RAR is power recycled, RAR will default to eSR 1.8V mode automatically. However at other times of RST_N, RAR may be in other mode (for example, qLR Linear Regulator and non 1.8V).
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Power Up and Reset Sequence 9. FW has to bring back RAR voltage regulator to eSR normal mode before it enables other SoC components for normal mode of operation. a. Set AON_VR.VREG_SEL to eSR/normal mode. b. Wait for 2 usec (TBC) for RAR to switch back to eSR normal mode delivering up to 50 mA max current. c. Clear AON_VR.ROK_BUF_VREG_MASK. 10. If (SCSS AON_VR.VSEL == 1.35V) { // exiting from 1.35V core voltage mode a. FW to set SCSS.AON_VR.VSEL = 0x10; // Set to 1.8V.
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Power Up and Reset Sequence One or more possible wake sources can be simultaneously enabled in a given low power state. RST_N assertion will automatically transition the SoC to normal/active state (4 MHz Si OSC mode) as given in section 9.1.1. Low Power State Possible Wake Sources Deep Sleep RTC state AON Periodic Timer (AONPT), RTC Alarm, GPIO Edge/Level triggered interrupt (with or without GPIO debouncing), Comparator, CLTAP Probe mode request through JTAG , RST_N assertion.
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Power Up and Reset Sequence 9.2.1 Active to Any Low Power State For those low power states not requiring voltage regulator to be put into retention mode, the following sequences are not required and can be handled by SW/FW by powering down or enabling clock gating of specific components not in use based on System Power State. For example, Low Power Halt state is mainly halting processor and optionally memory system by executing HALT instruction while peripherals can be in operation.
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Power Up and Reset Sequence 3. SW/FW must enable the needed interrupt sources for wake and mask all other interrupt sources. Wake sources can be any of enabled low power comparators, any GPIO based interrupt wake, AON Periodic Timer expiry, RTC alarm interrupt. Additionally system automatically wakes up to RST_N assertion. a. Program WAKE_MASK.WAKE_MASK[31:0], CCU_LP_CLK_CTL.WAKE_PROBE_MODE_MASK registers identical to Interrupt Mask registers. 4. Program HYB_OSC_PD_LATCH_EN = 0, RTC_OSC_PD_LATCH_EN=0.
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Power Up and Reset Sequence 11. FW to configure RAR Voltage regulator to operate in retention mode (Linear Regulator). This step is needed as RAR in eSR switching regulator mode is very inefficient (consumes more power) at low current loads. a. Set ROK_BUF_VREG_MASK as AON_VR.ROK_BUF_VREG would go low during retention mode. This ensures that logic that uses ROK_BUF_VREG output from RAR are not falsely triggered. b. Set AON_VR.VREG_SEL to qLR/retention mode. VSEL_IN is set to 1.8V.
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Power Up and Reset Sequence 9.2.2 Power Sequence Analog Characteristics The following table describes the analog characteristics of the blocks used in the SoC power sequences. Table 24.
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Power Up and Reset Sequence 9.3.1 Power On Reset The SoC provides an on-die circuitry to provide a power on reset when main power is applied. The power on reset is asserted when the SoC is powering up and is released when VCC_AON_1P8 has crossed a given threshold for a certain length of time. The only mechanism to trigger a power on reset is to remove and then re-apply main power. Only indication to SoC that power recycling happened is RST_N input pin.
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Power Up and Reset Sequence 9.3.2 Cold Reset A cold reset will trigger a power cycle of the Host domain (Processor Subsystem, Memory Subsystem, Peripheral Subsystem and Fabric) and trigger a reset of registers both in the Host and AON (SCSS) domains. There is no reset cycling of most of AON domain (SCSS) logic and also certain SCSS registers due to a cold reset. Table 25. Cold Reset Triggers Trigger Software writes 1 to RSTC.
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Power Up and Reset Sequence a. 4. Note that RSTC.WARM register bit gets cleared at WARM_RST#. Similarly watchdog timer, processor and other interrupt generation blocks are reset by warm reset. WARM_RST# is released. Note 1: Following interrupt sources are not to be redirected to trigger warm reset as they will not get cleared due to warm reset, leading to SoC permanently under warm reset. Only a power recycle or RST_N recycle will recover this condition. 1. 2. 3.
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Thermal Management 10 Thermal Management 10.1 Overview The Intel® Quark™ microcontroller D2000 SoC does not contain an integrated thermal sensor. Ambient temperature = -40°c to +85°c.
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Processor Core 11 Processor Core The SoC provides a single core x86 processor with separate and independent Tightly Coupled Memory (TCM) Interfaces for Instruction and Data. Figure 8. Processor Core IOs JTAG Local APIC Instruction TCM QuarkTM Core 32 IRQs Data TCM I/O APIC AHB-Lite 11.
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Processor Core • • • • Support for Paging included although not required for the Intel® Quark™ microcontroller D2000 use case o 2 Entry Instruction TLB (Translation Look-aside Buffer) o 2 Entry Data TLB (Translation Look-aside Buffer) Single cycle 32bx32b  32b Multiplier (IMUL Instruction) Integrated Intel® Quark™ microcontroller D2000 Interrupt Controller (MVIC) with support for 32 IRQs – some may be unused in Intel® Quark™ microcontroller D2000.
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Processor Core 11.2 Processor Memory Map The processor memory map for the Intel® Quark™ microcontroller D2000 SoC shall cater for the planned subsequent derivative SoCs which are likely to include variations in the amount of NVM and SRAM included in the SoC. Figure 8 shows the generic processor memory map that will be applicable to Intel® Quark™ microcontroller D2000 and its derivatives. Figure 9.
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Processor Core The CPU address map for Intel® Quark™ microcontroller D2000 is as follows: Notes: • • • • • • • • • • • • Reset Vector from CPU is mapped to 0x150 and falls into OTP Code region. OPEN: In which of the above regions will LMT implement “wrap-around-protect”? This is Lakemont Memory view – not Intel® Quark™ microcontroller D2000 Memory view. N1: LMT routes memory writes to Instruction* regions towards AHB. These writes are dropped by SoC’s Memory subsystem.
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Processor Core 11.3 Main Fabric Bus Cycle Processing The Lakemont CPU supports the following AHB-lite cycles: • • • Code Read Memory Read (Data) Memory Write (Data) The following sections describe the behavior of the SoC for all these supported types. 11.3.1.1 Code Reads Code Reads that fall within the I-TCM memory address range will be forwarded to the I-TCM interface. Code Reads outside of the ITCM range will be forwarded by default to the AHB-lite fabric, this includes code reads to the DTCM range.
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Processor Core Address on DTCM interface is 18b DW address. Hence, total DTCM address space is 1MB. Lowest 3 address bits are always driven to 0’s by the processor. Address, issued by LMT, on DTCM, is relative address and starts from offset 0 with respect to base address of 0x0028_0000. Only 512KB [0x0028_0000 to 0x002F_FFFF] is mapped to DTCM on LMT. LMT is an in-order machine with a single instruction in flight. AHB response in the fabric for a memory write makes the write on AHB-Lite interface posted.
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Processor Core If the processor generates a Flush Acknowledge Special cycle, it will be internally acknowledged to allow the processor to make forward progress but it will not appear on the AHB fabric or on any other external interface 11.3.1.5.3 Flush Special Cycle The Flush Special Cycle is generated by an x86 processor when an INVD instruction is executed.
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Processor Core Intel® Quark™ microcontroller D2000 does not assert STPCLK# and hence Stop Grant Acknowledge cycle is not generated by processor. 11.3.1.6 MSI The SoC AHB fabric will not send MSIs to the processor so an external interface for MSIs is not required. MSIs may be exchanged between the components within integrated MVIC. However, these MSIs remain internal to the processor sub-system and not no appear on the AHB fabric. BLV SoC does not assert NMI pin of LMT. 11.3.1.
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Processor Core Table 27.
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Processor Core 11.4 Intel® Quark™ microcontroller D2000 Interrupt Controller (MVIC) The Intel® Quark™ microcontroller D2000 programmable interrupt controller is based on an extension of the interrupt controller in Intel® Quark™ microcontroller D1000. The MVIC (Intel® Quark™ microcontroller D2000 Interrupt Controller) is configured by default to support 32 external interrupt lines. Unlike the traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and not programmable.
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Processor Core 11.4.1 MVIC Registers Table 29 enumerates all the programmable registers in the MVIC: Table 29: MVIC registers Memory Mapped Address FEE00080h FEE000A0h FEE000B0h FEE000F0h FEE00110h FEE00210h FEE00320h FEE00380h FEE00390h 11.4.1.1 Register Name TPR PPR EOI SIVR ISR IRR LVTTIMER ICR CCR Access R/W RO WO R/W RO RO R/W R/W RO TPR • • • • SW writes to this register with a line number to set a priority threshold.
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Processor Core 11.4.1.3 EOI The EOI is set when CPU initiates a write to address FEE000B0h. Upon receipt of the EOI write, the MVIC clears the highest-priority ISR bit, which corresponds to the interrupt that was just serviced. The MVIC ignores the actual value written to the EOI Register. 31 0 0/Ignored 11.4.1.4 SIVR SW writes the vector used for spurious interrupts to the SIVR 8 7 31 Reserved 11.4.1.
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Processor Core 11.4.1.6 IRR This register contains the active interrupt requests that have been accepted, but not yet dispatched to the core for servicing. When the MVIC accepts an interrupt, it sets the bit in the IRR that corresponds to the vector of the accepted interrupt. When the core is ready to handle the next interrupt, it will sent an INTA cycle and the MVIC clears the highest priority IRR (Interrupt Request Register) bit that is set and sets the corresponding ISR bit.
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Processor Core 11.4.1.8 ICR • • • • The initial count of the timer. The timer counts down from this value to 0. In periodic mode, the timer automatically reloads the Current Count Register (CCR) from the ICR when the count reaches 0. At this time, the MVIC generates a timer interrupt to the core and the countdown repeats. If during the countdown process software writes to the ICR, counting restarts using the new initial count value.
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Processor Core • SW can also read the index from the IOREGSEL register through the same bits 1,2,3,5 and 6. 31 7 6 5 4 3 1 0 Reserved • The IOWIN register has 2 bits per interrupt line (index) o Bit 15 : Trigger o Bit 16 : Mask 17 16 15 14 31 Reserved • • • 11.4.2 0 M T Reserved Trigger: Software sets this bit to configure the interrupt signal as level sensitive. Software clears this bit to configure the interrupt signal as edge sensitive.
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Processor Core 2. The latency for the first interrupt is close to what original LMT has. The latency to deliver subsequent interrupt of the same vector is much improved. The microcode latency is reduced to 21 cycles from 65 cycles. a. This optimization is only enabled in protected ring0 flat mode. i. CS, DS and SS base is 0 and corresponding limits are FFFF_FFFF b. This optimization employs an 32-entry look-aside table i.
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Processor Core 11.4.
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Processor Core 11.5 CPUID Note: Return value for EAX = 0x8000_000[2-4] does not contain “D2000” string.
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Memory Subsystem 12 Memory Subsystem The memory subsystem contains the following volatile and non-volatile memories: - System Flash OTP (implemented using Flash Memory) Internal System SRAM – 32KB – 8KB + 4 KB – 8KB Each of these regions implement protection mechanisms with access control described later. 12.1 Features 12.1.1 System Flash Controller Features - - - - The Flash controller interfaces with 32KB Main Memory Block and 8KB of Information Block of Flash memory.
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Memory Subsystem o o o Clk = 8MHz => 1 wait state on all accesses Clk = 16MHz => 1 wait state on all accesses Clk = 32MHz => 2 wait states on all accesses Clock Frequency ITCM Latency AHB Latency 32MHz 2 wait-states 2 wait-states 8-16MHz 1 wait-state 2 wait-states <= 4MHz 0/1 wait-state 1 wait-state Flash Protection mechanisms: The Flash Read Protection features are as follows: • • • • • There are 2 Agents: o Lakemont (determined by the AHB Master ID) o DMA (determined by the AHB Master ID
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Memory Subsystem • Support a scan mode where all the Flash control signals are gated during scan. The FPR registers reside in the Flash Controller Configuration Registers. The previously described protection is applied for ITCM requests also. 12.1.2 OTP Features - - 8KB OTP: o Implemented using the information memory region of Flash. o Part of Processor’s Instruction address space (ITCM). o Supports 64b wide reads via ITCM Interface. o Supports 32 bit wide reads via an AHB Lite Interface.
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Memory Subsystem 12.1.3 Internal SRAM Features - - - The internal SRAM controller presents 8KB of SRAM – organized in the form of 2 banks of 4KB each. Supports 64 bit wide reads and writes via a dedicated Host Processor DTCM Interface. Processor only reads and writes 32b at a time. Byte enables indicate which SRAM bank the request is targeting. All accesses are 64b address aligned. Supports 32 bit wide reads and writes via an AHB Lite Interface.
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Memory Subsystem • • When an Access Violation occurs a Violation Event trigger (Interrupt) is asserted and the following information is logged: The Agent, the Address and the Transfer Type (RD/WR) The Violation Event trigger is output as an interrupt - See Interrupt Routing for additional details relating to how this interrupt can be routed. Figure 10 Example IMR zones The IMR registers will reside in the SRAM Controller Configuration Registers.
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Memory Subsystem 12.2 Error Handling Scenario Notification Event Event Logging Data Handling ITCM Out of Range Read None None Read data returned is 32b value from register duplicated in lower and upper DW. ITCM Read Access Violation Interrupt Agent, QW Flash Address, Read data returned is 32b value from register duplicated in lower and upper DW. Type 6: 8KB OTP Read (ITCM); Type 7: 36KB Flash Read (ITCM). In case of concurrent violations from ITCM and AHB, AHB is higher priority than ITCM.
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Memory Subsystem Scenario Notification Event Event Logging Data Handling DTCM Out of Range Read None None Read data returned is 32b value from register duplicated in lower and upper DW. DTCM Read Access Violation Interrupt Agent, QW Address (bit2 undefined), Type. Read data returned is 32b value from register. Violations from DTCM and AHB are mutually exclusive. DTCM Out of Range Write None None Write data sent to SRAM with inactive BEs.
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Memory Subsystem • Case 2: CPU executing from 0x1FFF (end of OTP Instruction ROM). CPU prefetch can spill over to the reserved range 0x2000-0x7_FFFF. o The accesses to the reserved range will be completed. The SoC will return a fixed value of all Cs. o This will NOT be treated as an error condition and No spurious interrupts will be sent to the CPU. • Case 3: CPU executing from 0x18_7FFF (end of Instruction RAM). CPU prefetch can spill over to the reserved range 0x18_8000-0x1F_FFFF.
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Memory Subsystem 12.3 Memory Consistency Analysis The following illustration is the block diagram of the memory subsystem.
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Memory Subsystem Wait-state capability Fastest access limited by eFlash latency: 2 wait-state @ 32MHz  64b DTCM: Data TCM • Address range hardwired – see LMT-ULP Address Map later • Reads/Writes to DTCM address range • Wait-state capability  32b AHB-Lite: Peripheral interface • Master on AHB Lite interface • No AHB Slave port • No bursting capability • Code Reads to DTCM address range • Data reads/writes to ITCM address range • All probe mode accesses are issued on AHB • I/O reads/writes are unsupported
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Memory Subsystem •  • • • All DTCM writes and UC AHB reads (data accesses) must be in program order. • Same as A3 and A4 above except replace AHB write with AHB read. • AHB reads that are code accesses (e.g. to SRAM) have no ordering relationship with DTCM writes. Inside LMT, there is only a single data access outstanding at any time Flash Memory & Flash Controller: o Flash controller has 2 interfaces: ITCM and AHB Slave. o Flash Memory has asynchronous interface i.e. there is no clock input.
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Memory Subsystem • • • 12.3.1 o No locked transaction support. o One fabric interface for every master and slave. DMA o Separate Master and Slave interfaces on AHB interface o No write posting support i.e. all writes are non-posted. Slave Peripherals o Examples: UART, I2C, SPIC, etc. o No write posting support i.e. all writes are non-posted. o Single AHB slave interface to each peripheral. SCSS Configuration Registers o Control SoC configuration related to Clocks, Power Management, etc.
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Memory Subsystem Producer LMT LMT Consumer DMA LMT Data Flag SRAM SRAM SRAM AHB, LMT Interrupt AHB SRAM AHB AHB, LMT Interrupt SRAM SRAM, LMT Interrupt SRAM AHB AHB SRAM AHB AHB, LMT Interrupt Analysis DTCM writes from LMT are in-order and in program order. Since AHB fabric is in-order, DMA reads will observe data in same order. Hence, no memory consistency concerns. There is no posting buffer in SRAM controller on DTCM interface.
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Memory Subsystem Since prefetcher depth is only 128b and a long sequence of operations need to be performed to program flash memory, LMT’s prefetcher cannot contain stale instructions. Interaction of LMT’s instruction prefetcher vs Flash memory updates: From Intel® Quark™ microcontroller D2000’s usage model perspective, the routines to program/erase flash memory are part of boot code. It is an illegal usage model to modify this boot code while simultaneously executing from it. Hence, this is not a concern.
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Memory Subsystem Since AHB write to above register fields can be concurrent to ITCM code fetches, some form of synchronization is required to ensure ITCM interface is quiesced for these registers to alter SoC operation in a safe manner. It is possible to analyze the above 3 cases and find solutions. But a capability to control ITCM prefetching under specific conditions is a very useful capability that is lacking.
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Memory Subsystem 12.4.2 Flash Controller 0 Register Detailed Description 12.4.2.1 TMG_CTRL (TMG_CTRL) Flash Timing Control Register. There is a SW programming restriction for this register. When switching SoC to a higher frequency, this register must be updated first to reflect settings associated with higher frequency BEFORE SoC frequency is changed.
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Memory Subsystem Bits Access Type Default 9:6 RW 4'h1 Description PowerWell READ_WAIT_STATE_L (READ_WAIT_STATE_L) Flash SE low pulse width in system clocks plus one. This must be set to one when the system clock frequency is above 20 MHz. This determines when the Flash controller generates a read data valid indication and is based on the Flash data access time. 5:0 RW 6'h20 MICRO_SEC_CNT (MICRO_SEC_CNT) Number of clocks in a micro second. 12.4.2.
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Memory Subsystem Bits Access Type Default 1 RW/V 1'b0 Description PowerWell ER_REQ (ER_REQ) Erase request - set to '1' to trigger a ROM Page Erase. Check the FLASH_STTS.ER_DONE bit to determine when the erase completes. ER_REQ is self clearing. ER_REQ has no effect after CTRL.FL_WR_DIS has been written to 1'b1. Hardware blocks all erases after ROM has been programmed. 0 RW/V 1'b0 WR_REQ (WR_REQ) Write request - set WR_REQ to '1' to trigger a ROM write. Check the FLASH_STTS.
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Memory Subsystem 12.4.2.4 FLASH_WR_CTRL (FLASH_WR_CTRL) Flash Write Control Register Before issuing flash erase/program operation, 1. FW must disable all interrupts except the flash interrupt that indicates completion of erase/program operation. 2. Issue the MMIO write that triggers the program or erase operation. 3. Issue HALT instruction. As part of program/erase completion ISR, interrupts can be re-enabled.
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Memory Subsystem 12.4.2.5 FLASH_WR_DATA (FLASH_WR_DATA) Flash Write Data MEM Offset (B0100000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 10h False 32 bits 0000_0000h Description PowerWell DATA (DATA) Flash Write Data 12.4.2.
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Memory Subsystem 12.4.2.7 CTRL (CTRL) Control Register ROM below refers to 8KB OTP region only.
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Memory Subsystem Bits Access Type Default 1 RW 1'h0 Description PowerWell PRE_FLUSH (PRE_FLUSH) Prefetch buffer Flush 0 RW 1'h0 PRE_EN (PRE_EN) Prefetch Enable. When '1', prefetching is enabled. When '0', prefetching is disabled. 12.4.2.
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Memory Subsystem Bits Access Type Default 9:8 RO 2'h0 Description PowerWell RSV (RSV) Reserved 7:0 RW/L 8'h0 LWR_BOUND (LWR_BOUND) Upper 2 address bits of this register are unused by HW. The Lower Address Bound is compared with incoming Flash Address [15:10] to determine the lower 1KB aligned value of the Protected Region. For address comparison purposes, lower bits[9:0] are assumed to be all 0’s. Hence, incoming address is checked to be greater than or equal to this field. 12.4.2.
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Memory Subsystem Bits Access Type Default Description PowerWell Upper 2 address bits of this register are unused by HW. The Upper Address Bound is compared with incoming Flash Address [15:10] to determine the upper 1KB aligned value of the Protected Region. For address comparison purposes, lower bits[9:0] are assumed to be all 1’s. Hence, incoming address is checked to be less than or equal to this field.
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Memory Subsystem Bits Access Type Default Description PowerWell [2] : Enables Read Access for DMA [3] : Reserved 19:18 RO 2'h0 RSV1 (RSV1) Reserved 17:10 RW/L 8'h0 UPR_BOUND (UPR_BOUND) Upper 2 address bits of this register are unused by HW. The Upper Address Bound is compared with incoming Flash Address [15:10] to determine the upper 1KB aligned value of the Protected Region. For address comparison purposes, lower bits[9:0] are assumed to be all 1’s.
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Memory Subsystem Bits Access Type Default 23:20 RW/L 4'h0 Description PowerWell RD_ALLOW (RD_ALLOW) Enable Read Access on an Agent by Agent basis: [0] : Enables Read Access for the Host Processor [1] : Reserved [2] : Enables Read Access for DMA [3] : Reserved 19:18 RO 2'h0 RSV1 (RSV1) Reserved 17:10 RW/L 8'h0 UPR_BOUND (UPR_BOUND) Upper 2 address bits of this register are unused by HW.
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Memory Subsystem Bits Access Type Default 31 RW/1S 1'h0 Description PowerWell Valid (Valid) Lock out further writes to Flash 30:0 RO 31'h0 RSV (RSV) Reserved 12.4.2.13 MPR_VSTS (MPR_VSTS) Protection Status Register MEM Offset (B0100000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31 RW/1C/V 1'h0 30h False 32 bits 0000_0000h Description PowerWell VALID (VALID) This field is asserted when a Violation Event Occurs.
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Memory Subsystem Bits Access Type Default 17:0 RO/V 18'h0 Description PowerWell ADDR (ADDR) This field captures the invalid QW Flash Address that was detected during a violation. Upper 2 address bits are assumed to be all 0’s. Bit 2 is undefined. Lower 2 address bits are assumed to be all 0’s. 12.4.2.
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Memory Subsystem 12.4.4 Internal SRAM Register Detailed Description 12.4.4.
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Memory Subsystem Bits Access Type Default Description PowerWell Upper 4 bits are unused by HW. For address comparison purposes, lower address bits[9:0] of incoming address is assumed to be all 1’s. So, incoming address is checked for less than or equal to this field. 9:7 RO 3'b0 RSV1 (RSV1) Reserved 6:0 RW/L 7'b0 MPR Lower Bound (LWR_BOUND) The Lower Address Bound is compared with 16:10 of the incoming address determine the lower 1KB aligned value of the Protected Region.
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Memory Subsystem Bits Access Type Default 22:20 RW/L 3'b0 Description PowerWell MPR Write Access Allow (WR_ALLOW) Enable Write Access on an Agent by Agent basis: Bit [0] : Enables Write Access for the Host Processor Bit [1] : Reserved Bit [2] : Enables Write Access for DMA 19:17 RO 3'b0 RSV2 (RSV2) Reserved 16:10 RW/L 7'b0 MPR Upper Bound (UPR_BOUND) The Upper Address Bound is compared with 16:10 of the incoming address determine the upper 1KB aligned value of the Protected Region.
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Memory Subsystem Bits Access Type Default 30 RW/L 1'b0 Description PowerWell MPR Enable (ENABLE) Enable the Memory Protection Region 29:27 RO 3'b0 RSV4 (RSV4) Reserved 26:24 RW/L 3'b0 MPR Read Access Allow (RD_ALLOW) Enable Read Access on an Agent by Agent basis: [0] : Enables Read Access for the Host Processor [1] : Reserved [2] : Enables Read Access for DMA 23 RO 1'b0 RSV3 (RSV3) Reserved 22:20 RW/L 3'b0 MPR Write Access Allow (WR_ALLOW) Enable Write Access on an Agent by Agent ba
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Memory Subsystem 12.4.4.
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Memory Subsystem Bits Access Type Default 9:7 RO 3'b0 Description PowerWell RSV1 (RSV1) Reserved 6:0 RW/L 7'b0 MPR Lower Bound (LWR_BOUND) The Lower Address Bound is compared with 16:10 of the incoming address determine the lower 1KB aligned value of the Protected Region. Upper 4 bits are unused by HW. For address comparison purposes, lower address bits[9:0] of incoming address is assumed to be all 0’s. So, incoming address is checked for greater than or equal to this field. 12.4.4.
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Memory Subsystem Bits Access Type Default 30:20 RO 11'b0 Description PowerWell RSV (RSV) Reserved 19:18 RO/V 2'b0 MPR Violation Agent ID (AGENT) This field captures the Agent ID for an Access Violation: 0: Host Processor 1: Reserved 2: DMA 17 RO/V 1'b0 MPR Violation Agent ID (TYPE) This field captures the Transfer Type for an Access Violation: 0: Read 1: Write 16:0 RO/V 17'b0 MPR Violation Address (ADDR) This field captures the Address for an Access Violation.
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I2C 13 I2C The SoC implements one instance of an I2C controller, which can operate in master mode or slave mode as configured. Both 7 bit and 10 bit addressing modes are supported. 13.1 Signal Descriptions Please see Chapter 2, “Physical Interfaces” for additional details.
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I2C 13.3 • Hardware Handshake Interface to support DMA capability • Interrupt Control • FIFO support with 16B deep RX and TX FIFO’s Memory Mapped IO Registers Registers listed are for I2C 0, starting at base address B0002800h. Table 31.
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I2C MEM Address Default 0xB000285C 0000_0000h IC_CLR_ACTIVITY Clear ACTIVITY Interrupt 0xB0002860 0000_0000h IC_CLR_STOP_DET Clear STOP_DET Interrupt 0xB0002864 0000_0000h IC_CLR_START_DET Clear START_DET Interrupt 0xB0002868 0000_0000h IC_CLR_GEN_CALL Clear GEN_CALL Interrupt 0xB000286C 0000_0000h IC_ENABLE Enable 0xB0002870 0000_0006h IC_STATUS Status 0xB0002874 0000_0000h IC_TXFLR Transmit FIFO Level 0xB0002878 0000_0000h IC_RXFLR Receive FIFO Level 0xB000287C 0001_000
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I2C Bits Acces s Type Defaul t 31:1 0 RO 22'b0 9 RW 1'b0 Description PowerWel l ResetSigna l Reserved (RSV) RX_FIFO_FULL_HLD_CTRL (RX_FIFO_FULL_HLD_CTRL ) This bit controls whether the bus should be held when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Dependencies: This register bit value is applicable only when the IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1. If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only.
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I2C Bits Acces s Type Defaul t Description PowerWel l ResetSigna l 1: slave is disabled NOTE: Software must ensure slave and master mode are mutually exclusive. IMPORTANT: if IC_SLAVE_DISABLE == 0 -> MASTER_MODE == 0 5 RW 1'b1 Restart Support (IC_RESTART_EN) Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C controller operations.
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I2C Bits Acces s Type Defaul t 3 RW 1'b1 Description PowerWel l ResetSigna l Slave Addressing Mode (IC_10BITADDR_SLAVE) When acting as a slave, this bit controls whether the I2C controller responds to 7- or 10-bit addresses.
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I2C Bits Acces s Type Default 31:1 3 RO 19'h0000 1 12 RW 1'b0 Description PowerWel l ResetSigna l Reserved (RSV) IC_10BITADDR_MASTER (IC_10BITADDR_MASTER ) This bit controls whether the I2C controller starts its transfers in 7-or 10-bit addressing mode when acting as a master. 0: 7-bit addressing 1: 10-bit addressing 11 RW 1'b0 Special Command Enable (SPECIAL) This bit indicates whether software performs a General Call or START BYTE command.
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I2C Bits Acces s Type Default Description PowerWel l ResetSigna l This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex.
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I2C 13.3.1.4 High Speed Master ID (IC_HS_MADDR) I2C High Speed Master Mode Code Address. Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect. MEM Offset () Security_PolicyGroup IntelRsvd Size Default 0B000280Ch False 32 bits 0000_0001h Bits Access Type Default Description 31:3 RO 29'b0 Reserved (RSV) 2:0 RW 3'b01 HS Master Code (IC_HS_MAR) PowerWell ResetSignal This bit field holds the value of the I2C HS mode master code.
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I2C Bits Access Type Default Description PowerWell ResetSignal - 1 if IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
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I2C Bits Access Type Default Description PowerWell ResetSignal When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slavereceiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0].
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I2C 13.3.1.6 Standard Speed Clock SCL High Count (IC_SS_SCL_HCNT) Sets the SCL clock high-period count for standard speed (SS). Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
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I2C 13.3.1.7 Standard Speed Clock SCL Low Count (IC_SS_SCL_LCNT) Sets the SCL clock low-period count for standard speed (SS). Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
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I2C Bits Access Type Default Description PowerWell ResetSignal The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. 13.3.1.9 Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT) Sets the SCL clock low-period count for fast speed (FS). Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
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I2C 13.3.1.10 High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT) Sets the SCL clock high-period count for high speed (HS). Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
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I2C Bits Access Type Default Description PowerWell ResetSignal Must be set before any I2C bus transaction can take place to ensure proper I/O timing. For 100pF loading, the SCL High time is 60ns; for 400pF loading, the SCL High time is 120ns. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. 13.3.1.12 Interrupt Status (IC_INTR_STAT) Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register.
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I2C Bits Access Type Default 9 RO 1'b0 Description PowerWell ResetSignal Stop Detected (R_STOP_DET) Indicates whether a STOP condition has occurred on the I2C interface regardless of whether the controller is operating in slave or master mode. 8 RO 1'b0 Activity (R_ACTIVITY) This bit captures I2C controller activity and stays set until it is cleared.
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I2C Bits Access Type Default Description PowerWell ResetSignal NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes for transmission. 5 RO 1'b0 Read Requested (R_RD_REQ) This bit is set to 1 when I2C controller is acting as a slave and another I2C master is attempting to read data from it.
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I2C Bits Access Type Default Description PowerWell ResetSignal Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when IC_EN goes to 0, this interrupt is cleared.
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I2C Bits Access Type Default Description PowerWell ResetSignal Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when IC_EN goes to 0, this interrupt is cleared. 13.3.1.13 Interrupt Mask (IC_INTR_MASK) These bits mask their corresponding interrupt status bits.
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I2C Bits Access Type Default Description PowerWell ResetSignal Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether the controller is operating in slave or master mode. 9 RW 1'b0 Stop Detected Mask (M_STOP_DET) Indicates whether a STOP condition has occurred on the I2C interface regardless of whether the controller is operating in slave or master mode.
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I2C Bits Access Type Default Description PowerWell ResetSignal This bit indicates if the I2C controller, in transmitter mode, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
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I2C Bits Access Type Default Description PowerWell ResetSignal This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines.
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I2C Bits Access Type Default Description PowerWell ResetSignal Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The I2C Controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when IC_EN goes to 0, this interrupt is cleared.
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I2C Bits Access Type Default Description PowerWell ResetSignal Indicates whether a RESTART condition has occurred on the I2C interface when I2C controller is operating in slave mode and the slave is the addressed slave. 11 RO 1'b0 General Call Acknowledged (GEN_CALL) Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling the I2C controller or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register.
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I2C Bits Access Type Default Description PowerWell ResetSignal Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller is idle, this bit remains set until cleared, indicating that there was activity on the bus. 7 RO 1'b0 RX Completed (RX_DONE) When the I2C controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte.
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I2C Bits Access Type Default Description PowerWell ResetSignal This bit is set to 1 when I2C controller is acting as a slave and another I2C master is attempting to read data from it. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register.
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I2C Bits Access Type Default Description PowerWell ResetSignal Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
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I2C 13.3.1.15 Receive FIFO Threshold Level (IC_RX_TL) Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).
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I2C Bits Access Type Default Description PowerWell ResetSignal The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. 13.3.1.
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I2C 13.3.1.18 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER) Clear a single interrupt type. MEM Offset () Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RO 1'b0 0B0002844h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Clear RX_UNDER (CLR_RX_UNDER) Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT. 13.3.1.19 Clear RX_OVER Interrupt (IC_CLR_RX_OVER) Clear a single interrupt type.
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I2C Bits Access Type Default Description 31:1 RO 31'b0 Reserved (RSV) 0 RO 1'b0 Clear TX_OVER (CLR_TX_OVER) PowerWell ResetSignal Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT. 13.3.1.21 Clear RD_REQ Interrupt (IC_CLR_RD_REQ) Clear a single interrupt type.
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I2C Bits Access Type Default Description PowerWell ResetSignal Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. 13.3.1.23 Clear RX_DONE Interrupt (IC_CLR_RX_DONE) Clear a single interrupt type.
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I2C Bits Access Type Default 0 RO 1'b0 Description PowerWell ResetSignal Clear ACTIVITY (CLR_TX_ABRT) Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT.
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I2C Bits Access Type Default 31:1 RO 31'b0 0 RO 1'b0 Description PowerWell ResetSignal Reserved (RSV) Clear START_DET (CLR_START_DET) Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT. 13.3.1.27 Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL) Clear a single interrupt type.
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I2C Bits Access Type Default Description PowerWell ResetSignal The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation.
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I2C Bits Access Type Default Description PowerWell ResetSignal If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two I2C clocks delay when enabling or disabling the controller. 13.3.1.29 Status (IC_STATUS) Read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
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I2C Bits Access Type Default Description PowerWell ResetSignal NOTE: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. 4 RO 1'b0 Receive FIFO Completely Full (RFF) When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.
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I2C 13.3.1.30 Transmit FIFO Level (IC_TXFLR) Contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: The I2C is disabled, there is a transmit abort ( i.e. TX_ABRT bit is set in the IC_RAW_INTR_STAT register ) or the slave bulk transmit mode is aborted. The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
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I2C 13.3.1.32 SDA Hold (IC_SDA_HOLD) This register controls the amount of hold time on the SDA signal after a negative edge of SCL line in units of I2C clock period. The value programmed must be greater than the minimum hold time in each mode for the value to be implemented: 1 cycle in master, 7 cycles in slave mode. Writes to this register succeed only when I2C controller is disabled (IC_ENABLE=0).
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I2C Bits Acces s Type Defaul t Description PowerWel l 31:2 3 RO 9'b0 Reserved (TX_FLUSH_CNT) 22:1 7 RO 6'b0 Reserved (RSV) 16 RO 1'b0 ABRT_USER_ABRT (ABRT_USER_ABRT) ResetSigna l This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]). 15 RO 1'b0 Slave Read Completion (ABRT_SLVRD_INTX) Set if the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
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I2C Bits Acces s Type Defaul t Description PowerWel l ResetSigna l Set if master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 11 RO 1'b0 Master Disabled (ABRT_MASTER_DIS) Set if user tries to initiate a Master operation with the Master mode disabled.
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I2C Bits Acces s Type Defaul t Description PowerWel l ResetSigna l Set if the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. 7 RO 1'b0 START Acknowledged (ABRT_SBYTE_ACKDET) Set if master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
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I2C Bits Acces s Type Defaul t Description PowerWel l ResetSigna l Set if master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 1 RO 1'b0 10 Bit Address First Not Acknowledged (ABRT_10ADDR1_NOACK) Set if master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
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I2C 13.3.1.35 DMA Transmit Data Level Register (IC_DMA_TDLR) MEM Offset () Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:5 RO 27'b0 4:0 RW 5'h0 0B000288Ch False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Transmit Data Level (DMATDL) Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic.
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I2C Bits Access Type Default Description PowerWell ResetSignal The watermark level = DMARDL+1, signal is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE = 1. 13.3.1.37 SDA Setup (IC_SDA_SETUP) Controls the amount of time delay (in terms of number of I2C clock periods) introduced in the rising edge of SCL relative to SDA changing, by holding SCL low when servicing a read request while operating as a slave-transmitter.
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I2C 13.3.1.38 General Call Ack (IC_ACK_GENERAL_CALL) Controls whether the I2C controller responds with a ACK or NACK when it receives an I2C General Call address. MEM Offset () Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RW 1'h1 0B0002898h False 32 bits 0000_0001h Description PowerWell ResetSignal Reserved (RSV) I2C General Call Ack (ACK_GEN_CALL) When set to 1, the I2C controller responds with a ACK when it receives a General Call.
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I2C Bit s Acces s Type Defaul t Description PowerWe ll ResetSign al Indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the I2C controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.
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I2C Bit s Acces s Type Defaul t Description PowerWe ll ResetSign al When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.
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I2C Bits Access Type Default Description PowerWell 31:8 RO 24'b0 Reserved (RSV) 7:0 RW 8'h07 I2C SS and FS Spike Length (IC_FS_SPKLENRX_TL) ResetSignal Must be set before any I2C bus transaction can take place to ensure stable operation. 13.3.1.41 HS spike suppression limit (IC_HS_SPKLEN) Used to store the duration, measured in I2C clock cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in High Speed mode.
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I2C 13.3.1.42 Clear the RESTART_DET interrupt (IC_CLR_RESTART_DET) Read this register to clear the RESTART_DET interrupt. MEM Offset () Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RO 1'b0 0B00028A8h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Clear RESTART_DET (CLR_RESTART_DET) Read this register to clear the RESTART_DET interrupt. 13.3.1.
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I2C 13.3.1.45 Component Type (IC_COMP_TYPE) Register Offset IntelRsvd Size Default PowerWell 0B00028FCh True 32 bits 4457_0140h Bits Access Type Default 31:0 RO 4457_0140h Description PowerWell ResetSignal RSVD (RSVD) Reserved.
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UART 14 UART The SoC implements two instances of a 16550 compliant UART controller that supports baud rates between 300 baud and 2M baud. Hardware flow control is also supported. Both RS232 and RS485 are supported. 9-bit mode is also supported. 14.1 Signal Descriptions Table 32. Memory 0 or UART A Signals Signal Name Direction/ Type Description UART_A_TXD Logic output UART A single-ended Transmit data (RS232 or RS485). In RS485 mode, differential driver is outside SoC.
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UART Signal Name 14.2 Direction/ Type Description UART_B_DE Logic Output UART B Driver Enable (RS485 mode). Used to control the differential driver of RS485 in platform/board. This is multiplexed onto UART_B_RTS pin depending on RS485 or RS232 mode of operation. UART_B_RE Logic Output UART A Receiver Enable (RS485 mode). Used to control the differential receiver of RS485 in platform/board. This is multiplexed onto UART_B_CTS pin depending on RS485 or RS232 mode of operation.
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UART 14.3 Memory Mapped IO Registers Registers listed are for UART 0 or UART A, starting at base address B0002000h. UART 1 or UART B contains the same registers starting at base address B0002400h. Differences between the UARTs are noted in individual registers. Table 34.
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UART 14.3.1.1 Receive Buffer / Transmit Holding / Divisor Latch Low (RBR_THR_DLL) Receive Buffer Register(RBR), reading this register when the DLAB bit (LCR[7]) is zero; Transmit Holding Register (THR), writing to this register when the DLAB is zero; Divisor Latch Low (DLL), when DLAB bit is one.
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UART Bits Access Type Default Description PowerWell ResetSignal Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LSR) is set THR, Transmit Holding Register. Access - Write AND DLAB (LCR[7]) =0 Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode.
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UART 14.3.1.2 Interrupt Enable / Divisor Latch High (IER_DLH) Interrupt Enable Register (IER), when the DLAB bit is zero; Divisor Latch High (DLH), when the DLAB bit is one.
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UART Bits Access Type Default Description PowerWell ResetSignal This register makes up the upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. This register may be accessed only when the DLAB bit (LCR[7]) is set. Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur.
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UART Bits Access Type Default Description PowerWell ResetSignal 0000 = modem status. 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. NEVER INDICATED 1100 = character timeout. 4-5 RESERVED read as zero 6-7 FIFOSE, FIFOs Enabled. This is used to indicate whether the FIFO's are enabled or disabled: 00 = disabled 11 = enabled RESET VALUE FOR IIR = 0x01 FCR, FIFO Control Register Access - Write only Used to control the FIFOs.
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UART Bits Access Type Default Description PowerWell ResetSignal Resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. NOTE that this bit is 'selfclearing' and it is not necessary to clear this bit. 3 DMAM, DMA Mode 4-5 TET, TX Empty Trigger Used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active.
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UART 14.3.1.4 Line Control (LCR) Used to specify the format of the asynchronous data communication exchange. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:8 RO 24'b0 7 RW 1'h0 0B000200Ch False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Divisor Latch Access Bit (DLAB) Used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART.
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UART Bits Access Type Default Description PowerWell 2 RW 1'h0 Number of stop bits (STOP) ResetSignal Used to select the number of stop bits per character that the peripheral will transmit and receive. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted.
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UART 14.3.1.5 MODEM Control (MCR) Controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
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UART Bits Access Type Default Description PowerWell ResetSignal Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. 2 RW 1'h0 User designated Output 1 (OUT1) Used to directly control the user-designated Output1 (out1_n) output.
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UART Bits Access Type Default Description 0 RW 1'h0 Data Terminal Ready (DTR) PowerWell ResetSignal PowerWell ResetSignal Used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications.
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UART Bits Access Type Default Description PowerWell ResetSignal In the FIFO mode, since the 9th bit is associated with a character received, it is revealed when the character with the 9th bit set to 1 is at the top of the FIFO. Reading the LSR clears the 9BIT. NOTE: User needs to ensure that interrupt gets cleared (reading LSR register) before the next address byte arrives.
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UART Bits Access Type Default Description PowerWell ResetSignal If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled.
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UART Bits Access Type Default Description PowerWell ResetSignal Used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs the UART will try resynchronize.
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UART Bits Access Type Default 1 RO 1'h0 Description PowerWell ResetSignal Overrun error bit (OE) Used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten.
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UART 14.3.1.7 MODEM Status (MSR) Provides the current state of the control lines from the MODEM (or peripheral device). MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:8 RO 24'b0 7 RO 1'h0 0B0002018h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Data Carrier Detect (DCD) Used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n.
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UART Bits Access Type Default Description PowerWell ResetSignal Used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the UART. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR).
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UART Bits Access Type Default Description PowerWell ResetSignal Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit will get set when the reset is removed if the dcd_n signal remains asserted.
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UART Bits Access Type Default Description 0 RO 1'h0 Delta Clear to Send (DCTS) PowerWell ResetSignal PowerWell ResetSignal Used to indicate that the modem control line cts_n has changed since the last time the MSR was read. That is: 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one), DCTS reflects changes on MCR[1] (RTS).
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UART 14.3.1.9 UART Status (USR) Provides internal status information. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:5 RO 27'h0 4 RO 1'h0 0B000207Ch False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV1) Receive FIFO Full (RFF) Used to indicate that the receive FIFO is completely full. That is: 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full.
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UART Bits Access Type Default 0 RO 1'h0 Description PowerWell ResetSignal PowerWell ResetSignal Reserved (RSV0) 14.3.1.10 Halt Transmission (HTX) Halt Transmission. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RW 1'h0 0B00020A4h False 32 bits 0000_0000h Description Reserved (RSV) Halt Transmission (HTX) Used to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFO's are enabled.
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UART 14.3.1.11 DMA Software Acknowledge (DMASA) DMA software acknowledge if a transfer needs to be terminated due to an error condition. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RW 1'h0 0B00020A8h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) DMA Software Acknowledge (DMASA) Used to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition.
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UART Bits Access Type Default Description PowerWell ResetSignal 0 : In this mode, transmit and receive can happen simultaneously. The user can enable DE_EN, RE_EN at any point of time. Turn around timing as programmed in the TAT register is not applicable in this mode. 1 : In this mode, DE and RE are mutually exclusive. Either DE or RE only one of them is expected to be enabled through programming.
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UART Bits Access Type Default Description PowerWell ResetSignal Receiver Enable Polarity. 1: RE signal is active high 0: RE signal is active low 0 RW 1'h0 RS485 Transfer Enable (RS485_EN) RS485 Transfer Enable. 0 : In this mode, the transfers are still in the RS232 mode. All other fields in this register are reserved and registers DE_EN, RE_EN, DET and TAT are reserved. 1 : In this mode, the transfers will happen in RS485 mode. All other fields of this register are applicable. 14.3.1.
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UART 14.3.1.14 Receiver Output Enable Register (RE_EN) Receiver Output Enable Register. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 0 RW 1'h0 0B00020B4h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Receiver Output Enable (RE_Enable) The RE Enable register bit is used to control assertion and de-assertion of re signal. 0: De-assert RE signal 1: Assert RE signal 14.3.1.
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UART Bits Access Type Default 7:0 RW 8'h0 Description PowerWell ResetSignal DE assertion time (DE_assertion_time) DE signal assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the assertion of rising edge of Driver output enable signal to serial transmit enable. Any data in transmit buffer, will start on serial output (sout) after the transmit enable. 14.3.1.16 TurnAround Timing Register (TAT) TurnAround Timing Register.
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UART 14.3.1.17 Divisor Latch Fraction (DLF) Divisor Latch Fraction. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:4 RO 28'b0 3:0 RW 4'h0 0B00020C0h False 32 bits 0000_0000h Description PowerWell ResetSignal PowerWell ResetSignal Reserved (RSV) Divisor Latch Fraction (DLF) Register Divisor Latch Fraction (DLF) is used to store the Fractional part of BAUD divisor. 14.3.1.18 Receive Address Register (RAR) Receive Address Register.
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UART Bits Access Type Default Description PowerWell ResetSignal PowerWell ResetSignal NOTE: This register is applicable only when ADDR_MATCH (LCR[9]) and 'DLS_E' (LCR[8]) bits are set to 1. 14.3.1.19 Transmit Address Register (TAR) Transmit Address Register.
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UART 14.3.1.20 Line Extended Control Register (LCR_EXT) Line Extended Control Register. MEM Offset (B0002000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:4 RO 28'b0 3 RW 1'h0 0B00020CCh False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Transmit mode control bit (TRANSMIT_MODE) Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers.
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UART Bits Access Type Default Description PowerWell ResetSignal Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode. 1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what is being programmed in Transmit Address Register.
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UART Bits Access Type Default Description PowerWell ResetSignal NOTE: This field is applicable only when DLS_E is set to 1. 0 RW 1'h0 Extension for DLS (DLS_E) Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers.
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SPI 15 SPI The SoC implements two instances of a SPI controller. One controller supports Master operation and another controller supports Slave operation. 15.1 Signal Descriptions Please see Chapter 2, “Physical Interfaces” for additional details.
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SPI 15.
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SPI 15.3 Memory Mapped IO Registers Registers listed are for SPI Master 0, starting at base address B0001000h. SPI Slave 0 contains the same registers starting at base address B0001800h. Differences between the SPIs are noted in individual registers. Table 37.
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SPI MEM Address Default Name 0x68 0000_0000h DR2 Data Register 0x6C 0000_0000h DR3 Data Register 0x70 0000_0000h DR4 Data Register 0x74 0000_0000h DR5 Data Register 0x78 0000_0000h DR6 Data Register 0x7C 0000_0000h DR7 Data Register 0x80 0000_0000h DR8 Data Register 0x84 0000_0000h DR9 Data Register 0x88 0000_0000h DR10 Data Register 0x8C 0000_0000h DR11 Data Register 0x90 0000_0000h DR12 Data Register 0x94 0000_0000h DR13 Data Register 0x98 0000_0000h D
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SPI 15.3.1.1 Control Register 0 (CTRLR0) This register controls the serial data transfer. It is impossible to write to this register when the SPI Controller is enabled. The SPI Controller is enabled and disabled by writing to the SSIENR register.
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SPI Bits Access Type Default Description PowerWell ResetSignal When the SPI Controller is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back. 10 RW/L 1'h0 Slave Output Enable (SLV_OE) Relevant only when the SPI Controller is configured as a serial-slave device. When configured as a serial master, this bit field has no functionality.
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SPI Bits Access Type Default 9:8 RW/L 2'h0 Description PowerWell ResetSignal Transfer Mode (TMOD) Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receiveonly mode, transmitted data are not valid.
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SPI Bits Access Type Default 7 RW/L 1'h0 Description PowerWell ResetSignal Serial Clock Polarity (SCPOL) Valid when the frame format (FRF) is set to Motorola SPI*. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Controller master is not actively transferring data on the serial bus.
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SPI Bits Access Type Default 3:0 RO 4'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15.3.1.2 Control Register 1 (CTRLR1) This register exists only when the SPI Controller is configured as a master device. When the SPI Controller is configured as a serial slave, writing to this location has no effect; reading from this location returns 0. Control register 1 controls the end of serial transfers when in receive-only mode.
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SPI 15.3.1.3 SSI Enable Register (SSIENR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 08h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 0 RW 1'h0 SSI Enable (SSIENR) Enables and disables all SPI Controller operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled.
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SPI Bits Access Type Default 2 RW/L 1'h0 Description PowerWell ResetSignal Microwire Hanshaking (MHS) Relevant only when the SPI Controller is configured as a serial-master device. When configured as a serial slave, this bit field has no functionality. Used to enable and disable the 'busy/ready' handshaking interface for the Microwire protocol.
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SPI 15.3.1.5 Slave Enable Register (SER) This register is valid only when the SPI Controller is configured as a master device. When the SPI Controller is configured as a serial slave, writing to this location has no effect; reading from this location returns 0. The register enables the individual slave select output lines from the SPI Controller master. Up to 16 slave-select output signals are available on the SPI Controller master. You cannot write to this register when SPI Controller is busy.
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SPI 15.3.1.6 Baud Rate Select (BAUDR) This register is valid only when the SPI Controller is configured as a master device. When the SPI Controller is configured as a serial slave, writing to this location has no effect; reading from this location returns 0. The register derives the frequency of the serial clock that regulates the data transfer. The 16-bit field in this register defines the ssi_clk divider value. It is impossible to write to this register when the SPI Controller is enabled.
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SPI 15.3.1.7 Transmit FIFO Threshold Level (TXFTLR) This register controls the threshold value for the transmit FIFO memory. The SPI Controller is enabled and disabled by writing to the SSIENR register.
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SPI Bits Access Type Default 2:0 RW 3'h0 Description PowerWell ResetSignal Receive FIFO Threshold (RFT) Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. 15.3.1.
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SPI 15.3.1.10 Receive FIFO Level Register (RXFLR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:4 RO 28'b0 24h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 3:0 RO 4'h0 Receive FIFO Level (RXFLR) Contains the number of valid data entries in the receive FIFO. 15.3.1.
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SPI Bits Access Type Default 4 RO 1'h0 Description PowerWell ResetSignal Receive FIFO Full (RFF) When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0 : Receive FIFO is not full 1 : Receive FIFO is full 3 RO 1'h0 Receive FIFO Not Empty (RFNE) Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty.
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SPI 15.3.1.12 Interrupt Mask Register (IMR) This read/write register masks or enables all interrupts generated by the SPI Controller.
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SPI 15.3.1.13 Interrupt Status Register (ISR) This register reports the status of the SPI Controller interrupts after they have been masked.
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SPI 15.3.1.
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SPI 15.3.1.15 Transmit FIFO Overflow Interrupt Clear Register (TXOICR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 38h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 0 RO/C 1'h0 Clear Transmit FIFO Overflow Interrupt (TXOICR) This register reflects the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect. 15.3.1.
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SPI 15.3.1.17 Receive FIFO Underflow Interrupt Clear Register (RXUICR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'h0 40h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 0 RO/C 1'h0 Clear Receive FIFO Underflow Interrupt (RXUICR) This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect. 15.3.1.
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SPI 15.3.1.19 Interrupt Clear Register (ICR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'b0 48h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 0 RO/C 1'h0 Interrupt Clear Register (ICR) This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts. Writing to this register has no effect. 15.3.1.
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SPI 15.3.1.21 DMA Transmit Data Level (DMATDLR) MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:3 RO 29'h0 50h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 2:0 RW 3'h0 DMA Transmit Data Level (DMATDL) Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic.
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SPI 15.3.1.23 Identification Register (IDR) This read-only register is available for use to store a peripheral identification code. MEM Offset (B0001000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RO 32'h0 58h False 32 bits 0000_0000h Description PowerWell ResetSignal Identification Code (IDCODE) This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. 15.3.1.
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SPI 15.3.1.25 Data Register (DR0) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.27 Data Register (DR2) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.28 Data Register (DR3) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.30 Data Register (DR5) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.31 Data Register (DR6) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.33 Data Register (DR8) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.34 Data Register (DR9) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.36 Data Register (DR11) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.37 Data Register (DR12) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.39 Data Register (DR14) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.40 Data Register (DR15) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI 15.3.1.41 Data Register (DR16) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.43 Data Register (DR18) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.44 Data Register (DR19) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.46 Data Register (DR21) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.47 Data Register (DR22) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.49 Data Register (DR24) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.50 Data Register (DR25) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.52 Data Register (DR27) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.53 Data Register (DR28) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.55 Data Register (DR30) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.56 Data Register (DR31) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.58 Data Register (DR33) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
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SPI 15.3.1.59 Data Register (DR34) The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address locations of the memory map to facilitate AHB burst transfers.
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SPI Bits Access Type Default 31:16 RO 16'b0 Description PowerWell ResetSignal Reserved 1 (RSVD1) Reserved 15:0 RW 16'h0 Data Register (DR) When writing to this register, you must right-justify the data. Read data are automatically rightjustified. Read = Receive FIFO buffer Write = Transmit FIFO buffer 15.3.1.
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DMA Controller 16 DMA Controller The SoC contains a single 2-Channel DMA controller. The DMA controller supports Single or Multi-Block transfers from Memory to Memory, Peripheral to Memory, Memory to Peripheral or Peripheral to Peripheral. 16.1 Features The following is a list of the DMA Controller features: • • • • • • • • • 16.
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DMA Controller Interface ID Peripheral 10 Reserved 11 Reserved 12 I2C Master 0 TX 13 I2C Master 0 RX 14 Reserved 15 Reserved Transfer Type and Flow Control are configurable on a per Channel basis, the following Flow Control options are available depending on the Transfer Type: Table 39.
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DMA Controller In the event on an ERROR response the DMA transfer is cancelled and the corresponding channel is disabled, an Error Response interrupt will be generated if the channel configured to do so. 16.3 Memory Mapped IO Registers Registers listed are for the DMA Controller, starting at base address B0700000h.
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DMA Controller MEM Address Default 0xB07002D8 0000_0000h RAW_DST_TRAN Raw Status for IntDstTran Interrupt 0xB07002E0 0000_0000h RAW_ERR Raw Status for IntErr Interrupt 0xB07002E8 0000_0000h STATUS_TFR Status for IntTfr Interrupt 0xB07002F0 0000_0000h STATUS_BLOCK Status for IntBlock Interrupt 0xB07002F8 0000_0000h STATUS_SRC_TRAN Status for IntSrcTran Interrupt 0xB0700300 0000_0000h STATUS_DST_TRAN Status for IntDstTran Interrupt 0xB0700308 0000_0000h STATUS_ERR Status for IntE
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DMA Controller 16.3.1.1 Channel0 Source Address (SAR0) Source Address of DMA transfer The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.
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DMA Controller Updated after each destination transfer. The DINC field in the CTL0_L register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. 16.3.1.
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DMA Controller Bits Access Type Default Description 31:29 RO 3'b0 Reserved (RSV2) 28 RW 1'b0 LLP_SRC_EN (LLP_SRC_EN) PowerWell ResetSignal Block chaining is enabled on the source side only if the LLP_SRC_EN field is high and LLPx.LOC is non-zero 27 RW 1'b0 LLP_DST_EN (LLP_DST_EN) Block chaining is enabled on the destination side only if the LLP_DST_EN field is high and LLP0.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal 100 - Peripheral to Memory Peripheral ------------------------------------------------101 - Peripheral to Peripheral - Source Peripheral ------------------------------------------------110 - Memory to Peripheral Peripheral ------------------------------------------------111 - Peripheral to Peripheral - Destination Peripheral ------------------------------------------------19 RO 1'b0 Reserved (RSV0) 18 RW 1'b0 Destination
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Number of data items, each of width CTL0_L.SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change. 00 = Increment 01 = Decrement 1x = No change NOTE: Incrementing or decrementing is done for alignment to the next SRC_TR_WIDTH boundary.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Decoding for this field: Value - Size(bits) -------------------000 - 8 001 - 16 010 - 32 011 - 64 100 - 128 101 - 256 11x - 256 0 RW 1'b1 Interrupt enable (INT_EN) If set, then all interruptgenerating sources are enabled. Functions as a global mask bit for all interrupts for the channel. RAW interrupt registers still assert if INT_EN = 0. 16.3.1.
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DMA Controller Bits Acces s Type Default Description PowerWe ll ResetSign al List Item (LLI) in system memory at the end of the block transfer with the done bit set.Software can poll the LLI CTL0.DONE bit to see when a block transfer is complete. The LLI CTL0.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel.
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DMA Controller 16.3.1.6 Channel0 Source Status (SSTAT0) This register is a temporary placeholder for the source status information on its way to the SSTAT0 register location of the LLI. The source status information should be retrieved by software from the SSTAT0 register location of the LLI, and not by a read of this register over the DMAC slave interface.
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DMA Controller 16.3.1.
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DMA Controller 16.3.1.10 Channel0 Configuration LOWER (CFG_L0) Contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. You need to program this register prior to enabling the channel.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal 2. I2C = Active high 3. UART A/B = Active low 17:12 RO 6'b0 Reserved (RSV1) 11 RW 1'b1 Source Handshake select (HS_SEL_SRC) Used to select which handshake interface is active for source requests on this channel 0 = HW handshake. SW ones are ignored 1 = SW handshake.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal 0 = Not suspended. 1 = Suspend DMA transfer from the source. 7:5 RW 3'b0 Channel Priority (CH_PRIOR) Priority value equal to 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range: 0: 1 A programmed value outside this range will cause erroneous behavior. 4:0 RO 5'b0 Reserved (RSV0) 16.3.1.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Assigns a hardware handshaking interface (0-1) to the channel destination if the CFG0_L.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Destination status information is fetched only from the location pointed to by the DSTATAR0 register, stored in the DSTAT0 register and written out to the DSTAT0 location of the LLI if this field is high 4:2 RW 3'b001 AHB bus protocol bus control (PROTCTL) Protection Control bits used to drive the AHB HPROT[3:1] bus.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs.
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DMA Controller Bits Access Type Default 19:0 RW 20'b0 Description PowerWell ResetSignal Source Gather Interval (SGI) Specifies the source address increment/decrement in multiples of CTL0_L.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer. 16.3.1.13 Channel0 Destination Scatter (DSR0) The CTL0_L.DINC field controls whether the address increments or decrements.
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DMA Controller 16.3.1.14 Channel1 Source Address (SAR1) Source Address of DMA transfer The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Updated after each destination transfer. The DINC field in the CTL0_L register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. 16.3.1.
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DMA Controller 16.3.1.17 Channel1 Control LOWER (CTL_L1) Contains fields that control the DMA transfer It is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal 001 - Memory to Peripheral DMAC -------------------------------010 - Peripheral to Memory DMAC ---------------------------011 - Peripheral to Peripheral - DMAC -------------------------------100 - Peripheral to Memory Peripheral ------------------------------101 - Peripheral to Peripheral - Source Peripheral ------------------------------110 - Memory to Peripheral Peripheral ------------------------------111 - Peripheral to Per
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DMA Controller Bits Access Type Default 16:14 RW 3'b001 Description PowerWell ResetSignal Source Burst Transaction Length (SRC_MSIZE) Number of data items, each of width CTL0_L.SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface.
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DMA Controller Bits Access Type Default Description PowerWell 10:9 RW 2'b0 Source Address Increment (SINC) ResetSignal Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change. 00 = Increment 01 = Decrement 1x = No change NOTE: Incrementing or decrementing is done for alignment to the next SRC_TR_WIDTH boundary.
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DMA Controller Bits Access Type Default Description PowerWell 3:1 RW 3'b000 Destination transfer width (DST_TR_WIDTH) ResetSignal Decoding for this field: Value - Size(bits) -------------------000 - 8 001 - 16 010 - 32 011 - 64 100 - 128 101 - 256 11x - 256 0 RW 1'b1 Interrupt enable (INT_EN) If set, then all interruptgenerating sources are enabled. Functions as a global mask bit for all interrupts for the channel. RAW interrupt registers still assert if INT_EN = 0. 16.3.1.
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DMA Controller Bits Acces s Type Default Description PowerWe ll ResetSign al List Item (LLI) in system memory at the end of the block transfer with the done bit set.Software can poll the LLI CTL0.DONE bit to see when a block transfer is complete. The LLI CTL0.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel.
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DMA Controller 16.3.1.19 Channel1 Source Status (SSTAT1) This register is a temporary placeholder for the source status information on its way to the SSTAT0 register location of the LLI. The source status information should be retrieved by software from the SSTAT0 register location of the LLI, and not by a read of this register over the DMAC slave interface.
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DMA Controller 16.3.1.
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DMA Controller 16.3.1.23 Channel1 Configuration LOWER (CFG_L1) Contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. You need to program this register prior to enabling the channel.
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DMA Controller Bits Access Type Default Description PowerWell 17:12 RO 6'b0 Reserved (RSV1) 11 RW 1'b1 Source Handshake select (HS_SEL_SRC) ResetSignal Used to select which handshake interface is active for source requests on this channel 0 = HW handshake. SW ones are ignored 1 = SW handshake.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal 1 = Suspend DMA transfer from the source. 7:5 RW 3'b0 Channel Priority (CH_PRIOR) Priority value equal to 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range: 0: 1 A programmed value outside this range will cause erroneous behavior. 4:0 RO 5'b0 Reserved (RSV0) 16.3.1.24 Channel1 configuration UPPER (CFG_U1) Contains fields that configure the DMA transfer.
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DMA Controller Bits Access Type Default Description PowerWell 10:7 RW 4'h0 Source hardware interface (SRC_PER) ResetSignal Assigns a hardware handshaking interface (0-1) to the channel source if the CFG0_L.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal The AMBA Specification recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-toone mapping of these register bits to the HPROT[3:1] master interface signals.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data prefetching is disabled. 16.3.1.25 Channel1 Source Gather (SGR1) The CTL0_L.SINC field controls whether the address increments or decrements.
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DMA Controller 16.3.1.26 Channel1 Destination Scatter (DSR1) The CTL0_L.DINC field controls whether the address increments or decrements. For a fixed-address control, then the address remains constant throughout the transfer and this register is ignored.
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DMA Controller Bits Access Type Default 31:2 RO 30'b0 1:0 RW 2'b0 Description PowerWell ResetSignal Reserved (RSV) Raw Status for IntTfr Interrupt (RAW) Interrupt events are stored in this Raw Interrupt Status register before masking. Each bit in this register is cleared by writing a 1 to the corresponding location in the correspondent Clear register 16.3.1.28 Raw Status for IntBlock Interrupt (RAW_BLOCK) Block Transfer Complete Interrupt.
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DMA Controller 16.3.1.29 Raw Status for IntSrcTran Interrupt (RAW_SRC_TRAN) Source Transaction Complete Interrupt. Generated after completion of the last AHB transfer of the requested single/burst transaction from the handshaking interface (either the hardware or software handshaking interface) on the source side.
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DMA Controller Bits Access Type Default 31:2 RO 30'b0 1:0 RW 2'b0 Description PowerWell ResetSignal Reserved (RSV) Raw Status for IntDstTran Interrupt (RAW) Interrupt events are stored in this Raw Interrupt Status register before masking. Each bit in this register is cleared by writing a 1 to the corresponding location in the correspondent Clear register 16.3.1.31 Raw Status for IntErr Interrupt (RAW_ERR) Error Interrupt.
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DMA Controller 16.3.1.32 Status for IntTfr Interrupt (STATUS_TFR) DMA Transfer Complete Interrupt status MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:2 RO 30'b0 1:0 RO 2'b0 0B07002E8h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Status for IntTfr Interrupt (STATUS) Stores all interrupt events from channels after masking. One bit allocated per channel. Used to generate the DMAC interrupt signals 16.3.1.
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DMA Controller 16.3.1.34 Status for IntSrcTran Interrupt (STATUS_SRC_TRAN) Source Transaction Complete Interrupt status MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:2 RO 30'b0 1:0 RO 2'b0 0B07002F8h False 32 bits 0000_0000h Description PowerWell ResetSignal PowerWell ResetSignal Reserved (RSV) Status for IntSrcTran Interrupt (STATUS) Stores all interrupt events from channels after masking. One bit allocated per channel.
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DMA Controller 16.3.1.36 Status for IntErr Interrupt (STATUS_ERR) Error Interrupt status MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:2 RO 30'b0 1:0 RO 2'b0 0B0700308h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Status for IntErr Interrupt (STATUS) Stores all interrupt events from channels after masking. One bit allocated per channel. Used to generate the DMAC interrupt signals 16.3.1.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal Written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a readmodified write operation. 0 = masked 1 = unmasked 16.3.1.38 Mask for IntBlock Interrupt (MASK_BLOCK) Block Transfer Complete Interrupt mask. The contents of the Raw Status register is masked with the contents of the Mask register.
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DMA Controller 16.3.1.39 Mask for IntSrcTran Interrupt (MASK_SRC_TRAN) Source Transaction Complete Interrupt mask. The contents of the Raw Status register is masked with the contents of the Mask register.
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DMA Controller Mask for IntDstTran Interrupt (MASK_DST_TRAN) Destination Transaction Complete Interrupt mask. The contents of the Raw Status register is masked with the contents of the Mask register.
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DMA Controller Bits Access Type Default 31:10 RO 22'b0 9:8 RW 2'b0 Description PowerWell ResetSignal Reserved (RSV2) Interrupt Mask Write Enable (INT_MASK_WE) 0 = write disabled 1 = write enabled 7:2 RO 6'b0 Reserved (RSV1) 1:0 RW 2'b0 Mask for the interrupt (INT_MASK) Written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a readmodified write operation.
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DMA Controller 16.3.1.42 Clear for IntBlock Interrupt (CLEAR_BLOCK) Block Transfer Complete Interrupt clear MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:2 RO 30'b0 1:0 WO 2'b0 0B0700340h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Clear for Interrupt (CLEAR) 0 = no effect 1 = clear interrupt 16.3.1.
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DMA Controller 16.3.1.44 Clear for IntDstTran Interrupt (CLEAR_DST_TRAN) Destination Transaction Complete Interrupt clear MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:2 RO 30'b0 1:0 WO 2'b0 0B0700350h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV) Clear for Interrupt (CLEAR) 0 = no effect 1 = clear interrupt 16.3.1.
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DMA Controller 16.3.1.46 Combined Interrupt Status (STATUS_INT) The contents of each of the Status registers is ORed to produce a single bit for each interrupt type in this Combined Interrupt Status register.
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DMA Controller 16.3.1.
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DMA Controller Bits Access Type Default Description PowerWell 9:8 RW 2'b0 Destination Software Transaction Request write enable (DST_REQ_WE) ResetSignal 0 = write disabled 1 = write enabled 7:2 RO 6'b0 Reserved (RSV0) 1:0 RW 2'b0 Destination Transaction Request register (DST_REQ) This bit is written only if the corresponding channel write enable bit in the Write Enable field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN_REG register 16.3.1.
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DMA Controller Bits Access Type Default Description PowerWell ResetSignal This bit is written only if the corresponding channel write enable bit in the Write Enable field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN_REG register 16.3.1.
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DMA Controller 16.3.1.
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DMA Controller Bits Access Type Default Description 7:2 RO 6'b0 Reserved (RSV0) 1:0 RW 2'b0 Destination Last Transaction Request register (LSTDST) PowerWell ResetSignal This bit is written only if the corresponding channel write enable bit in the Write Enable field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN_REG register 16.3.1.
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DMA Controller Bits Access Type Default Description PowerWell 31:10 RO 22'b0 9:8 WO 2'b0 Channel enable register (CH_EN_WE) 7:2 RO 6'b0 Reserved (RSV0) 1:0 RW 2'b0 Channel enable register (CH_EN) ResetSignal Reserved (RSV1) Setting this bit enables a channel. Clearing this bit disables the channel. 0 = Disable the Channel 1 = Enable the Channel The CH_EN_REG.
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DMA Controller 16.3.1.56 DMA Test (DMA_TEST_REG) This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written. In normal operation, the readback value of some registers is a function of the DMA state and does not match the value written.
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DMA Controller 16.3.1.
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General Purpose I/O (GPIO) 17 General Purpose I/O (GPIO) The SoC contains a single instance of the GPIO controller. The GPIO controller provides a total of 25 GPIOs. 17.1 Signal Descriptions Please see Chapter 2, “Physical Interfaces” for additional details.
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General Purpose I/O (GPIO) Table 41. Summary of GPIO Registers—0xB0000C00 MEM Address 17.3.1.
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General Purpose I/O (GPIO) Bits Access Type Default 25:0 RW 26'b0 Description PowerWell ResetSignal Port Data (GPIO_SWPORTA_DR) Values written to this register are output on the I/O signals for if the corresponding data direction bits are set to Output mode and the corresponding control bit for the Port is set to Software mode. The value read back is equal to the last value written to this register 17.3.1.
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General Purpose I/O (GPIO) 17.3.1.
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General Purpose I/O (GPIO) Bits Access Type Default 25:0 RW 26'b0 Description PowerWell ResetSignal Interrupt Enable (GPIO_INTEN) Allows each bit of Port A to be configured for interrupts. By default the generation of interrupts is disabled. Whenever a 1 is written to a bit of this register, it configures the corresponding bit on Port A to become an interrupt; otherwise, Port A operates as a normal GPIO signal.
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General Purpose I/O (GPIO) Bits Access Type Default Description PowerWell ResetSignal Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking.
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General Purpose I/O (GPIO) 17.3.1.7 Interrupt Polarity (GPIO_INT_POLARITY) Controls the interrupt polarity associated with Port A bits configured as interrupt sources MEM Offset (B0000C00) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:26 RO 6'b0 25:0 RW 26'b0 0B0000C3Ch False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV0) Interrupt Polarity (GPIO_INT_POLARITY) Controls the polarity of edge or level sensitivity that can occur on input of Port A.
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General Purpose I/O (GPIO) Bits Access Type Default 25:0 RO 26'b0 Description PowerWell ResetSignal Interrupt Status (GPIO_INTSTATUS) After mask. See GPIO_RAW_INTSTATUS for raw interrupt values and GPIO_INTMASK for interrupt mask configuration 17.3.1.
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General Purpose I/O (GPIO) Bits Access Type Default Description PowerWell ResetSignal PowerWell ResetSignal Controls whether an external signal that is the source of an interrupt needs to be debounced to remove any spurious glitches. Writing a 1 to a bit in this register enables the debouncing circuitry. A signal must be valid for two periods of an external clock before it is internally processed. 0 No debounce (default) 1 Enable debounce 17.3.1.
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General Purpose I/O (GPIO) 17.3.1.12 Port A External Port (GPIO_EXT_PORTA) Used by the software to read values from the GPIO Port bits MEM Offset (B0000C00) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:26 RO 6'b0 25:0 RO 26'b0 0B0000C50h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV0) External Port (GPIO_EXT_PORTA) When the Port is configured as Input, then reading this location reads the values on the external signal.
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General Purpose I/O (GPIO) 17.3.1.14 Interrupt both edge type (GPIO_INT_BOTHEDGE) Controls the edge type of interrupt that can occur on Port A MEM Offset (B0000C00) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:26 RO 6'b0 25:0 RW 26'b0 0B0000C68h False 32 bits 0000_0000h Description PowerWell ResetSignal Reserved (RSV0) Interrupt both edge type (GPIO_PWIDTH_A) Controls the edge type of interrupt that can occur on Port A.
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General Purpose I/O (GPIO) 17.3.1.15 GPIO Configuration Register 2 (GPIO_CONFIG_REG2) Stores the bit Port width minus one Register Offset IntelRsvd Size Default PowerWell 0B0000C70h True 32 bits 0003_9C73h Bits Access Type Default 31:0 RO 0003_9C73h Description PowerWell ResetSignal RSVD (RSVD) Reserved 17.3.1.
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Timers and PWM 18 Timers and PWM The Timer and Pulse Width Modulation (PWM) block allows individual control of the frequency and duty cycle of two output signals. The PWM block also supports use as a Timer block for the purposes of generating periodic interrupts. 18.1 Signal Descriptions Please see Chapter 2, “Physical Interfaces” for additional details.
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Timers and PWM • 18.2.1  Interrupt Mask Capability Timer Mode o 32-bit Timer operating at 32MHz  Timer Periods from 1 32MHz clock period (31.25ns) to 2^32-1 32MHz clock periods (134s) o Interrupt Control per Timer:  Interrupt Generation on Timer Expiry  Interrupt Mask Capability PMW Signaling The Timer and PWM block supports the generation of PWM Output signals with configurable low and high times which allows both the duty cycle and frequency to be set.
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Timers and PWM Table 43. PWM Timing Characteristic Value (System Clock Cycles) Value (time) Low Time Granularity 1 31.25ns Low Time Range 2 to 4294967296 (2^32) 62.5ns to 134.22s High Time Granularity 1 31.25ns High Time Range 2 to 4294967296 (2^32) 62.5ns to 134.22s See Section 18.3.1 for details on configuring the low and high times. PWM Mode supports the following maskable interrupt source: • Both edges of the PWM Output signal.
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Timers and PWM 18.3.2 Timer Mode When a timer counter is enabled after being reset or disabled, the count value is loaded from the TimerNLoadCount register; this occurs in both free-running and userdefined count modes. When a timer counts down to 0, it loads one of two values, depending on the timer operating mode: • • User-defined count mode – Timer loads the current value of TimerNLoadCount or TimerNLoadCount2 register alternatingly.
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Timers and PWM 0xB00008A0 0000_0000h TimersIntStatus Timers Interrupt Status 0xB00008A4 0000_0000h TimersEOI Timers End Of Interrupt 0xB00008A8 0000_0000h TimersRawIntStatus Timers Raw (unmasked) Interrupt Status 0xB00008AC 3230_392Ah TimersCompVersion Timers Component Version 0xB00008B0 0000_0000h Timer1LoadCount2 Timer 1 Load Count 2 0xB00008B4 0000_0000h Timer2LoadCount2 Timer 2 Load Count 2 18.4.1.
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Timers and PWM In both PWM and Timer mode, reading this register field returns the current value of the counter controlling the PWM/Timer. If reading from this register outside of an interrupt service routine, software should first perform 2 dummy writes to another PWM/Timer register. 18.4.1.
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Timers and PWM Intel® Quark™ microcontroller D2000 Datasheet 354 January 2016 Document Number: 333577-002EN
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Timers and PWM 18.4.1.4 Timer 1 End Of Interrupt (Timer1EOI) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bit s Acces s Type Defaul t 31: 1 RO 31'h0 0 RO 0B000080Ch False 32 bits 0000_0000h Description PowerWel l ResetSigna l PowerWel l ResetSigna l Reserved (RSVD1) Reserved 1'h0 Timer End-of-Interrupt (TIMER_END_OF_INTERRUP T) Reading from this register returns b0, and clears the interrupt form PWM/Timer. 18.4.1.
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Timers and PWM 18.4.1.6 Timer 2 Load Count (Timer2LoadCount) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 0B0000814h False 32 bits 0000_0000h Description PowerWell ResetSignal Timer Load Count (TimerLoadCount) In PWM mode, this register field controls the low period of pwm_o. In timer mode, this is the value that the timer counter starts counting down from, and controls the high and low periods of pwm_o. 18.4.1.
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Timers and PWM 18.4.1.8 Timer 2 Control (Timer2ControlReg) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bit s Acces s Type Defaul t 31:4 RO 28'h0 0B000081Ch False 32 bits 0000_0000h Description PowerWel l ResetSigna l Reserved (RSVD1) Reserved 3 RW 1'h0 Timer PWM (TIMER_PWM) Select between PWM mode and Timer mode.
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Timers and PWM Bit s Acces s Type Defaul t 31: 1 RO 31'h0 0 RO Description PowerWel l ResetSigna l PowerWel l ResetSigna l Reserved (RSVD1) Reserved 1'h0 Timer End-of-Interrupt (TIMER_END_OF_INTERRUP T) Reading from this register returns b0, and clears the interrupt form PWM/Timer. 18.4.1.
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Timers and PWM 18.4.1.11 Timers Interrupt Status (TimersIntStatus) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bit s Access Type Default 31: 8 RO 24'h0 7:0 RO 0B00008A0h False 32 bits 0000_0000h Description PowerWel l ResetSign al PowerWe ll ResetSign al Reserved (RSVD1) Reserved 8'h0 Timers Interrupt Status (TIMERS_INTERRUPT_STA TUS) A read of this register returns the post masking interrupt status of PWM/Timer's 0 to 7. Bit corresponds to PWM/Timer.
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Timers and PWM 18.4.1.13 Timers Raw (unmasked) Interrupt Status (TimersRawIntStatus) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bit s Acces s Type Defau lt 31: 8 RO 24'h0 7:0 RO 0B00008A8h False 32 bits 0000_0000h Description PowerW ell ResetSign al Reserved (RSVD1) Reserved 8'h0 Timers Raw Interrupt Status (TIMERS_RAW_INTERRUPT_STA TUS) A read of this register returns the pre masking interrupt status of all PWM/Timers. Bit position corresponds to PWM/Timer.
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Timers and PWM 18.4.1.15 Timer 1 Load Count 2 (Timer1LoadCount2) MEM Offset (B0000800) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 0B00008B0h False 32 bits 0000_0000h Description PowerWell ResetSignal PowerWell ResetSignal Timer Load Count 2 (TimerLoadCount2) In PWM mode, this register field controls the high period of pwm_o. In timer mode, this register has no functional use. 18.4.1.
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Watchdog Timer 19 Watchdog Timer The Watchdog Timer can be used to trigger a Warm Reset in the event that the SoC has become unresponsive. 19.1 Features The following is a list of the Watchdog (WDT) features: • • • • 19.1.
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Watchdog Timer 7 223 262.144ms 8 224 524.288ms 9 225 1.049s 10 226 2.097s 11 227 4.194s 12 228 8.389s 13 229 16.777s 14 230 33.554s 15 231 67.109s • 19.2 Use When enabled the timer starts counting down from the programmed Timeout Value. If the processor fails to reload the counter before it reaches zero (timeout) the WDT will do one of two things depending on the programmed Response Mode: Table 47.
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Watchdog Timer Table 48. Summary of WDT Registers—0xB0000000 MEM Address 19.3.1.
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Watchdog Timer Bits Access Type Default Description PowerWell Response mode 0 = Generate a system reset 1 = First generate interrupt if not cleared generate reset 0 RW 1'h0 WDT Enable (WDT_ENABLE) WDT Enable 0 = WDT Disable 1 = WDT Enable 19.3.1.
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Watchdog Timer 19.3.1.3 Current Counter Value Register (WDT_CCVR) MEM Offset (B0000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'hFFFF 8h False 32 bits 0000_FFFFh Description PowerWell Current Counter Value Register (WDT_CCVR) This register when read is the current value of the internal counter 19.3.1.
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Watchdog Timer 19.3.1.6 Interrupt Clear Register (WDT_EOI) MEM Offset (B0000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'h0 14h False 32 bits 0000_0000h Description PowerWell Reserved (RSVD1) Reserved 0 RO 1'h0 Interrupt Clear Register (WDT_EOI) Clears the watchdog interrupt. This can be used to clear the interrupt without restarting the watchdog counter 19.3.1.
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Watchdog Timer 19.3.1.9 Component Parameters (WDT_COMP_PARAM_3) Register Offset IntelRsvd Size Default PowerWell 0ECh True 32 bits 0000_0000h Bits Access Type Default 31:0 RO 0000_0000h Description PowerWell RSVD (RSVD) Reserved 19.3.1.10 Component Parameters (WDT_COMP_PARAM_2) Register Offset IntelRsvd Size Default PowerWell 0F0h True 32 bits 0000_0000h Bits Access Type Default 31:0 RO 0000_0000h Description PowerWell RSVD (RSVD) Reserved 19.3.1.
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Watchdog Timer 19.3.1.12 Component Version Register (WDT_COMP_VERSION) Register Offset IntelRsvd Size Default PowerWell 0F8h True 32 bits 3130_372Ah Bits Access Type Default 31:0 RO 3130_372Ah Description PowerWell RSVD (RSVD) Reserved 19.3.1.
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Real Time Clock (RTC) 20 Real Time Clock (RTC) The SoC contains a Real Time Clock for the purpose of keeping track of time. The RTC operates from 1 Hz to 32.768 kHz. The RTC supports alarm functionality that allows scheduling an Interrupt / Wake Event for a future time. The RTC operates in all SoC Power States. The RTC is powered from the same battery supply as the rest of the SOC and does not have its own dedicated supply. 20.
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Real Time Clock (RTC) 20.2.1 RTC Clock The RTC clock is the output of a 4bit prescaler (see Clocking Section) that is driven by the output of the 32.768 kHz Crystal Oscillator. This allows a range of clock frequencies to be generated as shown in the table below: Table 50. RTC Clock Scaling Scaling factor 20.2.2 Output Clock Frequency 0 32.768 kHz 1 16.384 kHz 2 8.192 kHz 3 4.096 kHz 4 2.048 kHz 5 1.
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Real Time Clock (RTC) For accessing any registers in RTC block, both APN Clock (pclk) and counter clock (rtcclk) should be running and the frequency of the APB Bus clock must be greater than three times the frequency of the counter clock.
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Real Time Clock (RTC) 20.3.2 Alarm Alarm functionality is provided by the Match Value Register, the interrupt generation logic asserts the interrupt (if enabled) when the Counter reaches this Match Value. The RTC allows the user to disable interrupt generation and also to mask a generated interrupt. Additionally the RTC supports generation of an interrupt when only the RTC clock is running, this allows the interrupt to be generated when in the Deep Sleep state. 20.3.
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Real Time Clock (RTC) 20.4 Memory Mapped IO Registers Registers listed are for RTC, starting at base address B000400h. Table 51.
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Real Time Clock (RTC) Bits Access Type Default 31:0 RO 32'h0 Description PowerWell Current Counter Value Register (RTC_CCVR) This register when read is the current value of the internal counter January 2016 Document Number: 333577-002EN Intel® Quark™ microcontroller D2000 Datasheet 375
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Real Time Clock (RTC) 20.4.1.2 Current Match Register (RTC_CMR) MEM Offset (B0000400) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 4h False 32 bits 0000_0000h Description PowerWell Current Match Register (RTC_CMR) When the internal counter matches this register and interrupt is generated, provided interrupt generation is enabled 20.4.1.
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Real Time Clock (RTC) 20.4.1.
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Real Time Clock (RTC) 20.4.1.6 Interrupt Raw Status Register (RTC_RSTAT) MEM Offset (B0000400) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 RO 31'h0 14h False 32 bits 0000_0000h Description PowerWell Reserved (RSVD1) Reserved 0 RO 1'h0 RTC RSTAT (RTC_RSTAT) This register is the raw interrupt status 0 = interrupt is inactive 1 = interrupt is active 20.4.1.
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Real Time Clock (RTC) 20.4.1.
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Comparators 21 Comparators The SOC supports 19 Low power comparators which can be used to wake the system from low power states. Two types of comparators are supported, a Low power, low performance version and a high power high performance version. Analog Inputs [5:0] are connected to high performance comparators and Analog Inputs [18:6] are connected to low power comparators. Each comparator can be powered down to achieve even lower power.
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Comparators 21.2 Features The following is a list of comparator features: • • • • • • • 21.3 2.0V – 3.63V AVDD operation 1.2V – 1.98V DVDD operation Fast Asynchronous comparator 1 Positive and 2 negative inputs with selectable digital input Rail to rail input range CMPLP o <3.8us propagation delay o <600nA static current o <10mV hysteresis (6 mV typ) o <22nA power down current CMPHP o <0.25us propagation delay o <9.8uA static current o <6.8mV hysteresis (4.6 mV typ) o <2.
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Comparators 2) Clear CMP_STAT_CLR for each firing comparator by writing a ‘1’ If the external analog input generates a pulse matching polarity level of CMP_REF_POL for sufficient duration greater than comparator’s propagation delay, interrupt gets latched. If external input maintains its signal state to that of CMP_REF_POL, interrupt persists and is not cleared even if CMP_STAT_CLR is applied. The comparators are directly connected to the PMU logic in the always on domain of the SOC.
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Analog to Digital Convertor (ADC) 22 Analog to Digital Convertor (ADC) The SoC implements a Successive-Approximation (SAR) Analog to Digital Convertor (ADC) which is capable of taking 19 single-ended analog inputs for conversion. ADC is characterized to operate over the AVDD (1.8 to 3.6 V) analog input range. 22.1 Signal Descriptions Please see Chapter 2, “Physical Interfaces” for additional details.
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Analog to Digital Convertor (ADC) • Current Consumption: o ~18 uA at 10 kSPS o ~240 uA at 1 MSPS o ~1.1 mA at 5 MSPS o ~15 uA standby o ~2 uA powerdown Notes: 1. 2. 3. 22.3 ADC Hard macro takes in adcclk in the range of 140 kHz to 32 MHz. Minimum clock frequency is 140 kHz. adcclk is derived from system clock by configuring CCU_PERIPH_CLK_DIV_CTL0.CCU_ADC_CLK_DIV register in SCSS. ADC Hard macro at its max sampling rate takes selres resolution + 2 cycles.
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Analog to Digital Convertor (ADC) DPD Deep Power Down mode. ADC is disabled, calibration state is lost, DVDD can be off. Enadc=L, enldo=L, dislvl=H. exit involves waiting for internal voltage regulator to start-up + recalibration + dummy conversion cycle. A complete calibration cycle lasts 81 clock cycles. A conversion cycle is 14 CLK cycles for 12bit resolution. 1 uA @ avdd, 0.5 uA @ dvdd - 10 usec + 95 CLK cycles.
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Analog to Digital Convertor (ADC) 22.4 Memory Mapped IO Registers Registers listed are for ADC, starting at base address B0004000h. Table 54.
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Analog to Digital Convertor (ADC) Bits Access Type Default Description PowerWell ResetSignal Subsequent conversions will begin at the start of the table. 30:29 RO 2'h0 RSVD (RSVD) Reserved 28:24 RW 5'h0 Channel[4N+3] (Channel_3) ADC Channel: this bit field defines the ADC channel to sample 23 RW 1'h1 Last[4N+2] (Last_2) Last Channel when set, this bit indicates that this is the last channel in the sequence. Subsequent conversions will begin at the start of the table.
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Analog to Digital Convertor (ADC) Bits Access Type Default Description PowerWell ResetSignal Reserved 4:0 RW 5'h0 Channel[4N+0] (Channel_0) ADC Channel: this bit field defines the ADC channel to sample 22.4.1.2 ADC Command Register (ADC_CMD) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default 20h False 32 bits 0000_0000h This register returns 0x0 value when ADC Calibration & Conversion is in IDLE state waiting for a new command.
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Analog to Digital Convertor (ADC) Bits Acces s Type Defau lt 22:1 6 RW 7'h0 Description PowerW ell ResetSign al CDI - Calibration Data Input (CDI) when the ADC command is a load calibration command, this bit field defines the digital offset calibration data to be loaded. 15:1 4 RW 2'h0 Resolution (Resolution) This bit field defines the number of bits of precision.
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Analog to Digital Convertor (ADC) Bits Acces s Type Defau lt Description PowerW ell ResetSign al 4 = Load calibration 5 = Stop continuous conversion 6 = No operation 7 = No operation 22.4.1.
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Analog to Digital Convertor (ADC) Bits Access Type Default 0 RW/1C 1'h0 Description PowerWell ResetSignal PowerWell ResetSignal CC - Command Complete except for Continuous Mode (CC) when read, a 1 indicates that an ADC command except for Continuous Mode has completed since the bit was last reset. When written, a 1 clears the bit. 22.4.1.
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Analog to Digital Convertor (ADC) 22.4.1.5 ADC Sample Register (ADC_SAMPLE) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 2Ch False 32 bits 0000_0000h Description PowerWell ResetSignal ADC Sample (Sample) when read, this bit-field contains the ADC sample. A read unloads one sample from the FIFO. The FIFO is flushed on a write. 22.4.1.
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Analog to Digital Convertor (ADC) 22.4.1.7 ADC FIFO Count Register (ADC_FIFO_COUNT) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default 34h False 32 bits 0000_0000h Bits Access Type Default Description 31:6 RO 26'h0000000 PowerWell ResetSignal RSVD (RSVD) Reserved 5:0 RO 6'h0 ADC FIFO Count (FifoCount) when read, this bit-field contains the number of samples stored in the ADC FIFO. Writing has no effect. 22.4.1.
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Analog to Digital Convertor (ADC) Bits Access Type Default 23:16 RO 8'h00 Description PowerWell ResetSignal RSVD (RSVD) Reserved 15:3 RW 13'd500 Delay (Delay) writing to this bit field along with operating mode sets the delay between mode transitions in system clock cycles. Reading this bit field returns the current delay value. 2:0 RW 3'h0 OM - Operating Mode (OM) writing to this bit field along with delay initiates a change in the operating mode.
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Interrupt Routing 23 Interrupt Routing The Interrupt Routing consists of several elements: 1. 2. 3. 4. Internal Host Processor Interrupts SoC Interrupts with configurable routing to Processor Capability for SoC Interrupts to trigger a Processor Halt for Debug Capability for SoC Interrupts to trigger a Warm Reset 23.1 Interrupt Routing 23.1.1 Host Processor Interrupts The Interrupt Vector Assignments for the Host Processor are described in Table 53: Table 55.
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Interrupt Routing Interrupt Vectors 0 to 31 are due to events internal to the Host Processor, interrupts due to SoC events are routed through the User Defined Interrupts. The User Defined Interrupts are delivered to the Host Processor via the PIC which maps particular Interrupt Inputs (IRQs) to configured Interrupt Vectors before presenting the interrupt to the Processor. The SoC Interrupt table shows the IRQ number into the PIC rather than the hardwired Interrupt Vector. 23.1.
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Interrupt Routing Interrupt Source Interrupt Source Description Host Processor IRQ No. Host Processor Halt for Debug Int. SRAM Controller Int. SRAM Controller Internal SRAM Memory Protection Error Single Interrupt 49 Y Int. Flash Controller 0 Int.
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System Control Subsystem 24 System Control Subsystem The System Control Subsystem (SCSS) contains functional blocks that control power sequencing, clock generation, reset generation, interrupt routing and pin muxing. 24.
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System Control Subsystem 24.2 Memory Mapped IO Registers Registers listed are for the SCSS, starting at base address B0800000h. Table 57.
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System Control Subsystem MEM Address Default Instance Name Name 0xB0800328 0000_0000h CMP_STAT_CLR Comparator clear register 0xB0800448 0001_0001h INT_I2C_MST_0_MASK Host Processor Interrupt Routing Mask 0 0xB0800454 0001_0001h INT_SPI_MST_0_MASK Host Processor Interrupt Routing Mask 2 0xB080045C 0001_0001h INT_SPI_SLV_MASK Host Processor Interrupt Routing Mask 4 0xB0800460 0001_0001h INT_UART_0_MASK Host Processor Interrupt Routing Mask 5 0xB0800464 0001_0001h INT_UART_1_MASK Ho
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System Control Subsystem MEM Address Default Instance Name Name 0xB0800714 0000_0000h AONPT_CFG Always on periodic timer configuration register 0xB0800804 0000_0000h PERIPH_CFG0 Peripheral Configuration 0xB0800810 0000_0000h CFG_LOCK Configuration Lock 0xB0800900 00D0_0000h PMUX_PULLUP Pin Mux Pullup 0xB0800910 0000_0000h PMUX_SLEW Pin Mux Slew Rate 0xB0800920 03FF_FFFFh PMUX_IN_EN Pin Mux Input Enable 0x930 0000_0000h PMUX_SEL[0] Pin Mux Select 0x934 0000_0000h PMUX_SEL[1
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System Control Subsystem 24.3 Register Detailed Description 24.3.1.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal OSC0_CFG0[20:19]: 00b: Default bias current to Gm mos in crystal oscillator 01b: Increase bias current by 23% 10b: Decrease bias current by 23% 11b: Increase bias current by 46% OSC0_CFG0[18:17]: 00b: Default fixed cap in cap trim array crystal oscillator 01b: Increase fixed cap by 19% 10b: Decrease fixed cap by 38% 11b: Increase fixed cap by 38% OSC0_CFG0[16]: Unused 15:8 RW/P/L 8'h0 Test Mode Inputs (OSC0_HYB_SET
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal 01b: Zero bias current 10b: Make the bias current 1.5 times its default value 11b: Make the bias current 0.5 times its default value OSC0_CFG0[9:8]: 00b: Default bias current to comparator 01b: Zero bias current 10b: Make the bias current 1.5 times its default value 11b: Make the bias current 0.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal 1b: Select external start up for compensated current reference OSC0_CFG0[2]: 0b: Default cut start up current of both current references 1b: Disable cutting the start up branch current OSC0_CFG0[1]: 0b: Normal operation of silicon oscillator 1b: Trimming operation of silicon oscillator OSC0_CFG0[0]: 0b: silicon oscillator works in normal mode (supply = 1.8V) 1b: silicon oscillator works in retention mode (supply = 1.
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System Control Subsystem 24.3.1.3 Hybrid Oscillator configuration 1 (OSC0_CFG1) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:30 RO 2'h0 8h False 32 bits 0000_0302h Description PowerWell ResetSignal RSVD (RSVD) Reserved 29:20 RW/P/L 10'h0 Trim Code (OSC0_FTRIMOTP) 10 bit trim code from OTP 19:16 RW/P/L 4'h0 Crystal oscillator trim bits (OSC0_FADJ_XTAL) Trim Code corresponding to load capacitance on board.
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System Control Subsystem Bits Access Type Default 14:13 RW/P/L 2'h0 Description PowerWell ResetSignal Oscillator 0 Temperature Control (OSC0_TEMPCOMPPRG) Bits to control the temperature compensation of silicon oscillator 00b: Default temperature compensation 01b: Default temperature compensation 10b: Reduce PTAT current in temperature compensation 11b: Increase PTAT current in temperature compensation 12:10 RW/P/L 3'h0 Oscillator 0 bias current Control (OSC0_IBIASPRG) Bits to control the bias
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System Control Subsystem Bits Access Type Default 2 RW/P/L 1'h0 Description PowerWell Oscillator 0 Power-down control (OSC0_PD) ResetSignal pwr_rst_n 0b: Oscillator in active mode 1b: Oscillator in power down mode 1 RW/P 1'h1 Silicon Oscillator Enable (OSC0_EN_SI_OSC) When High Enables The Silicon Oscillator 0 RW/P 1'h0 Crystal Oscillator Enable (OSC0_EN_CRYSTAL) When High Enables The Crystal Oscillator 24.3.1.
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System Control Subsystem 24.3.1.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal 110b: Count 4915 cycles (150ms) 111b: Count 21299 cycles (650ms) OSC1_CFG0[3]: 0b: Gate output of oscillator with LOCK signal 1b: Give out oscillator output directly OSC0_CFG0[2]: Unused 1 RW/P/L 1'h0 Power down signal for crystal oscillator (OSC1_PD) pwr_rst_n 1b: disable 0b: enable 0 RW/P/L 1'h0 RTC Enable Bypass mode (OSC1_BYP_XTAL_UP) 1b: enable 0b: disable 24.3.1.
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System Control Subsystem Bits Access Type Default 21:2 0 RO 2'h0 19 RW/P Description PowerWell ResetSignal RSVD (RSVD) Reserved 1'b1 I2C master 0 pclk clock gate enable (CCU_I2C_M0_PCLK_EN_S W) 1b: enable 0b: disable 18 RW/P 1'b1 UART B pclk clock gate enable (CCU_UARTB_PCLK_EN_SW ) 1b: enable 0b: disable 17 RW/P 1'b1 UART A pclk clock gate enable (CCU_UARTA_PCLK_EN_SW ) 1b: enable 0b: disable 16 RW/P 1'b1 SPI slave pclk clock gate enable (CCU_SPI_PCLK_EN_SW) 1b: enable 0b: disable
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System Control Subsystem Bits Access Type Default 10 RW/P 1'b1 Description PowerWell ResetSignal Watch Dog Timer clock gate enable (CCU_WDT_PCLK_EN_SW) 1b: enable 0b: disable 9 RO 1'h0 RSVD (RSVD) Reserved 8 RW/P 1'b1 General Purpose IO Debounce Clock Enable (CCU_PERIPH_GPIO_DB_CL K_EN) 1b: enable 0b: disable 7 RW/P 1'b1 General Purpose IO interrupt Clock Enable (CCU_GPIO_INTR_CLK_EN) 1b: enable 0b: disable 6 RO 1'h0 RSVD (RSVD) Reserved 5 RW/P 1'b1 SPI Master 0 clock enable (C
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System Control Subsystem Bits Access Type Default 0 RW/P 1'b1 Description PowerWell ResetSignal PERIPH_HCLK_EN (CCU_PERIPH_HCLK_EN) This controls the peripheral hclk clock which is given to periph icm & AHB2APB Bridge. 1b: enable 0b: disable 24.3.1.
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System Control Subsystem 24.3.1.
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System Control Subsystem 24.3.1.
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System Control Subsystem 24.3.1.10 System Low Power Clock Control (CCU_LP_CLK_CTL) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Acces s Type Defaul t 31:1 7 RO 15'h000 0 16 RW/P 1'b1 2Ch False 32 bits 0001_F000h Description PowerW ell ResetSign al RSVD (RSVD) Reserved Clock gate Enable for AON_CNT (CCU_AON_TMR_CNT_CLK_EN _SW) Clock gate Enable for AON_CNT.
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System Control Subsystem Bits Acces s Type Defaul t 12:8 RW/P 5'b1000 0 Description PowerW ell ResetSign al CCU CPU Halt Clock Count (CCU_CPU_HALT_CLK_CNT) This defines the number of clock cycles clock can be gated whenever cpu executes halt instruction. 7:5 RO 3'h0 RSVD (RSVD) Reserved 4 RW/P 1'b0 CCU LP Exit to Hybrid Oscillator (CCU_EXIT_TO_HYBOSC) This is provided to control the mux between hybrid oscillator and RTC oscillator for sys_clk at the time of exiting low power state.
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System Control Subsystem 24.3.1.11 Wake Mask register (WAKE_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW/P/L 32'hFFFFFFFF 30h False 32 bits FFFF_FFFFh Description PowerWell ResetSignal Wake Mask register (WAKE_MASK) Wake Mask Enable for corresponding 32 irq sources.
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System Control Subsystem 24.3.1.12 AHB Control Register (CCU_MLAYER_AHB_CTL) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:7 RO 25'h000000 0 6 RW/P 1'b0 34h False 32 bits 0000_0014h Description PowerWell ResetSignal RSVD (RSVD) Reserved DMA Clock enable (CCU_DMA_CLK_EN) This controls clock to DMA Controller. By default clock to DMA controller is disabled.
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System Control Subsystem 24.3.1.
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System Control Subsystem Bits Access Type Default Description 2 RW/P/L 1'b1 RTC Clock Divider Enable (CCU_RTC_CLK_DIV_EN ) PowerWell ResetSignal This bit must be written from 0 -> 1 to apply the value 1 RW/P/L 1'b1 RTC Clock Enable (CCU_RTC_CLK_EN) 1b: enable 0b: disable 0 RW/P 1'b1 Select Clock (CCU_SYS_CLK_SEL) 0b: 32 kHz RTC Crystal Oscillator 1b: 32 MHz Hybrid Oscillator 24.3.1.
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System Control Subsystem Bits Access Type Default 27 RW/1S 1'h0 Description PowerWell 10 bit trim code from OTP Lock (OSC0_FTRIMOTP_LOCK) ResetSignal pwr_rst_n 1b: Lock 26 RW/1S 1'h0 Crystal oscillator trim bits Lock (OSC0_FADJ_XTAL_LOCK) pwr_rst_n 1b: Lock 25 RW/1S 1'h0 Oscillator 0 Temperature Control Lock (OSC0_TEMPCOMPPRG_LOCK ) pwr_rst_n 1b: Lock 24 RW/1S 1'h0 Oscillator 0 bias current Control Lock (OSC0_IBIASPRG_LOCK) pwr_rst_n 1b: Lock 23 RW/1S 1'h0 Oscillator 0 start-up
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System Control Subsystem Bits Access Type Default 12 RW/1S 1'h0 Description PowerWell OSC1 Powerdown Lock (OSC1_PD_LOCK) ResetSignal pwr_rst_n 1b: Lock 11 RW/1S 1'h0 OSC0 Powerdown Lock (OSC0_PD_LOCK) pwr_rst_n 1b: Lock 10:0 RO 11'h000 RSVD (RSVD) Reserved 24.3.1.
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System Control Subsystem 24.3.1.16 SoC Control Register Lock (SOC_CTRL_LOCK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default 44h False 32 bits 0000_0000h Bit s Access Type Default 31: 1 RO 31'h0000_00 00 0 RW/1S 1'b0 Description PowerWell ResetSignal RSVD (RSVD) Reserved Override OTP Security Lock (OVR_OTP_SEC_LOCK ) pwr_rst_n Lock OVR_OTP_SEC Field in OVR_OTP_SEC register. 24.3.1.
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System Control Subsystem 24.3.1.18 General Purpose Sticky Register 1 (GPS1) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default 104h False 32 bits 0000_0000h Bits Access Type Default Description PowerWell 31:0 RW/P 32'h0 Sticky scratchpad 1 (GPS1) ResetSignal Cleared on POR or COLD reset 24.3.1.
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System Control Subsystem 24.3.1.21 General Purpose Scratchpad Register 0 (GP0) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 114h False 32 bits 0000_0000h Description PowerWell ResetSignal General Purpose Scratchpad Register 0 (GP0) Cleared on POR or COLD or WARM reset 24.3.1.
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System Control Subsystem 24.3.1.24 General Purpose Scratchpad Register 3 (GP3) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RW 32'h0 120h False 32 bits 0000_0000h Description PowerWell ResetSignal General Purpose Scratchpad Register 3 (GP3) Cleared on POR or COLD or WARM reset 24.3.1.
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System Control Subsystem 24.3.1.27 Comparator enable (CMP_EN) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:19 RO 13'h0000 300h False 32 bits 0000_0000h Description PowerWell ResetSignal RSVD (RSVD) Reserved 18:0 RW/P 19'h0 Comparator enable (CMP_EN) If en: 0b comparator interrupt will not fire. 24.3.1.
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System Control Subsystem 24.3.1.29 Comparator reference polarity select register (CMP_REF_POL) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:19 RO 13'h0000 308h False 32 bits 0000_0000h Description PowerWell ResetSignal RSVD (RSVD) Reserved 18:0 RW/P 19'h0 Comparator reference polarity select register (CMP_REF_POL) 0b: Comparator monitors if Analog input voltage is greater than voltage reference.
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System Control Subsystem 24.3.1.31 Comparator clear register (CMP_STAT_CLR) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:19 RO 13'h0000 328h False 32 bits 0000_0000h Description PowerWell ResetSignal RSVD (RSVD) Reserved 18 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_18) The current status of the latched value of the comparator. Software must clear the latch before another interrupt.
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System Control Subsystem Bits Access Type Default 15 RW/1C/V/P 1'h0 Description PowerWell ResetSignal Comparator status clear register (CMP_STAT_CLR_15) The current status of the latched value of the comparator. Software must clear the latch before another interrupt. Each Bit of This Register Manages Over One Out of Nineteen Comparators. For Each Comparator: 1b: clear 14 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_14) The current status of the latched value of the comparator.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal Each Bit of This Register Manages Over One Out of Nineteen Comparators. For Each Comparator: 1b: clear 11 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_11) The current status of the latched value of the comparator. Software must clear the latch before another interrupt. Each Bit of This Register Manages Over One Out of Nineteen Comparators.
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System Control Subsystem Bits Access Type Default 8 RW/1C/V/P 1'h0 Description PowerWell ResetSignal Comparator status clear register (CMP_STAT_CLR_8) The current status of the latched value of the comparator. Software must clear the latch before another interrupt. Each Bit of This Register Manages Over One Out of Nineteen Comparators. For Each Comparator: 1b: clear 7 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_7) The current status of the latched value of the comparator.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal Each Bit of This Register Manages Over One Out of Nineteen Comparators. For Each Comparator: 1b: clear 4 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_4) The current status of the latched value of the comparator. Software must clear the latch before another interrupt. Each Bit of This Register Manages Over One Out of Nineteen Comparators.
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System Control Subsystem Bits Access Type Default 1 RW/1C/V/P 1'h0 Description PowerWell ResetSignal Comparator status clear register (CMP_STAT_CLR_1) The current status of the latched value of the comparator. Software must clear the latch before another interrupt. Each Bit of This Register Manages Over One Out of Nineteen Comparators. For Each Comparator: 1b: clear 0 RW/1C/V/P 1'h0 Comparator status clear register (CMP_STAT_CLR_0) The current status of the latched value of the comparator.
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System Control Subsystem Bits Access Type Default 15:1 RO 15'h000 0 0 RW/P/L 1'b1 Description PowerWell ResetSignal RSVD (RSVD) Reserved I2C Master 0 Host interrupt mask (INT_I2C_MST_0_HOST_MAS K) 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem 24.3.1.34 Host Processor Interrupt Routing Mask 4 (INT_SPI_SLV_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:1 7 RO 15'h000 0 16 RW/P/L 1'b1 45Ch False 32 bits 0001_0001h Description PowerWell ResetSignal RSVD (RSVD) Reserved SPI Slave Host Halt interrupt mask (INT_SPI_SLV_HOST_HALT_ MASK) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem Bits Access Type Default Description PowerWell 16 RW/P/L 1'b1 UART0 Master Halt interrupt mask (INT_UART_0_HOST_HAL T_MASK) ResetSignal 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.HALT_INT_REDIR 1: Masked 15:1 RO 15'h0000 RSVD (RSVD) Reserved 0 RW/P/L 1'b1 UART0 Master interrupt mask (INT_UART_0_HOST_MAS K) 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem 24.3.1.38 Host Processor Interrupt Routing Mask 9 (INT_TIMER_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Acces s Type Defaul t 31:1 7 RO 15'h000 0 16 RW/P/ L 1'b1 470h False 32 bits 0001_0001h Description PowerWe ll ResetSign al RSVD (RSVD) Reserved Timer Host Halt interrupt mask (INT_TIMER_HOST_HALT_MA SK) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem 24.3.1.39 Host Processor Interrupt Routing Mask 11 (INT_RTC_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Acces s Type Default 31:1 7 RO 15'h000 0 16 RW/P/L 1'b1 478h False 32 bits 0001_0001h Description PowerWe ll ResetSign al RSVD (RSVD) Reserved RTC Host Halt interrupt mask (INT_RTC_HOST_HALT_MAS K) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem Bits Acce ss Type Defaul t Description PowerW ell 16 RW/P/ L 1'b1 Watchog Host Halt interrupt mask (INT_WATCHDOG_HOST_HALT_ MASK) ResetSig nal 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.HALT_INT_REDIR 1: Masked 15:1 0 RO RW/P/ L RSVD (RSVD) 15'h00 00 Reserved Watchog Host interrupt mask (INT_WATCHDOG_HOST_MASK) 1'b1 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem Bits Acce ss Type Defau lt Description PowerW ell 31:1 9 RO 13'h00 00 RSVD (RSVD) 18:0 RW/P/ L 19'h7ff ff Comparators Host Halt interrupt mask (INT_COMPARATORS_HOST_HALT _MASK) ResetSig nal Reserved 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.HALT_INT_REDIR 1: Masked 24.3.1.
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System Control Subsystem 24.3.1.45 Host Processor Interrupt Routing Mask 26 (INT_HOST_BUS_ERR_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bit s Acce ss Type Defau lt 31:1 7 RO 15'h00 00 16 RW/P/ L 1'b1 4B4h False 32 bits 0001_0001h Description PowerW ell ResetSig nal RSVD (RSVD) Reserved Host Processor Bus Error Host Halt mask (INT_HOST_BUS_ERR_HOST_HAL T_MASK) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem Bits Acce ss Type Defaul t Description PowerW ell 17:1 6 RW/P/ L 2'b11 DMA Error Host Halt Mask - 2 bits (INT_DMA_ERROR_HOST_HALT_ MASK) ResetSig nal 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.HALT_INT_REDIR 1: Masked 15:2 1:0 RO RW/P/ L RSVD (RSVD) 14'h00 00 Reserved DMA Error Host Mask - 2 bits (INT_DMA_ERROR_HOST_MASK) 2'b11 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem 24.3.1.48 Host Processor Interrupt Routing Mask 29 (INT_FLASH_CONTROLLER_0_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bit s Acce ss Type Defa ult 31: 17 RO 15'h00 00 16 RW/P /L 1'b1 4C0h False 32 bits 0001_0001h Description Power Well ResetSi gnal RSVD (RSVD) Reserved Flash Controller 0 Host Halt interrupt mask (INT_FLASH_CONTROLLER_0_HOST_ HALT_MASK) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem Bits Acce ss Type Defaul t Description PowerW ell 16 RW/P/ L 1'b1 Always-On Timer Host Halt Interrupt Mask (INT_AON_TIMER_HOST_HALT_ MASK) ResetSig nal 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.HALT_INT_REDIR 1: Masked 15:1 0 RO RW/P/ L 15'h00 00 1'b1 RSVD (RSVD) Reserved Always-On Timer Host Interrupt Mask (INT_AON_TIMER_HOST_MASK) 0: Interrupt Event triggers interrupt to host processor 1: Masked 24.3.1.
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System Control Subsystem 24.3.1.51 Host Processor Interrupt Routing Mask 33 (INT_ADC_CALIB_MASK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Acce ss Type Defaul t 31:1 7 RO 15'h00 00 16 RW/P/ L 1'b1 4D0h False 32 bits 0001_0001h Description PowerW ell ResetSig nal RSVD (RSVD) Reserved ADC Conversion/Calibration int Host Halt Interrupt Mask (INT_ADC_CALIB_HOST_HALT_ MASK) 0: Interrupt Event triggers a warm reset or entry into probe mode based on P_STS.
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System Control Subsystem Bit s Acces s Type Default Description PowerWe ll 2 RW/1S 1'b0 Lock All Host Processor Halt Mask Fields (LOCK_HOST_HALT_MAS K) 1 RO 1'h0 RSVD (RSVD) ResetSign al pwr_rst_n Reserved 0 RW/1S 1'b0 Lock All Host Processor Interrupt Mask Fields (LOCK_HOST_MASK) pwr_rst_n 24.3.1.
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System Control Subsystem Bits Access Type Default 8 RW/P/L 1'h0 Description PowerWell ResetSignal Volatge Regulator Select during low power state. (VREG_SEL) 0: eSR Switching Regulator is kept enabled during low power state. 1: eSR Switching Regulator disabled and qLR Linear Regulator enabled (retention mode) 7:6 RO 2'h0 RSVD (RSVD) Reserved 5 RW/P/L 1'h0 Voltage Select Strobe (VSTRB) Enables output voltage programming using VSEL, minimum high pulse width requirement is 1us.
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System Control Subsystem Bits Access Type Default Description PowerWell ResetSignal 11100b : 3.00V 11101b : 3.10V 11110b : 3.20V 11111b : 3.30V Values between 00000b and 00111b are illegal. 24.3.1.
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System Control Subsystem 24.3.1.55 Processor Status (P_STS) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:27 RO 5'h00 560h False 32 bits 0000_0000h Description PowerWell ResetSignal RSVD (RSVD) Reserved 26 RW/P/L 1'h0 Halt Interrupt Redirection (HALT_INT_REDIR) When an enabled host halt interrupt occurs, this bit determines if the interrupt event triggers a warm reset or an entry into Probe Mode.
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System Control Subsystem Bits Access Type Default Description PowerWell 2 RW/1C/V/P 1'h0 Processor Shutdown (SHDWN) ResetSignal Status bit indicating the processor has issued a Shutdown special cycle. A Shutdown special cycle is generated when the processor incurs a double fault. The processor remains in Shutdown mode until it is reset. This bit is set when the Shutdown special cycle is issued and can only be cleared by software.
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System Control Subsystem Bits Access Type Default 31:4 RO 28'h0000000 Description PowerWell ResetSignal RSVD (RSVD) Reserved 3 RW/P 1'h0 Cold Reset (COLD) When this bit is set, the SoC performs a cold reset. 2 RO 1'h0 RSVD (RSVD) Reserved 1 RW 1'h0 Warm Reset (WARM) When this bit is set, the SoC performs a warm reset.
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System Control Subsystem 24.3.1.57 Reset Status (RSTS) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:6 RO 26'h000000 0 5 RW/1C/V/ P 1'h0 574h False 32 bits 0000_0000h Description PowerWel l ResetSigna l RSVD (RSVD) Reserved Processor Bus Error (BUS_ERR) Status bit indicating that an error response has been observed on the processor bus.
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System Control Subsystem Bits Access Type Default 0 RW/1C/V/ P 1'h0 Description PowerWel l ResetSigna l Software Initiated Warm Reset (SW_WRST) When this bit is set, it indicates that warm reset was initiated by software writing to RSTC.WARM. 24.3.1.
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System Control Subsystem 24.3.1.59 Always on counter register (AONC_CNT) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RO/V/P 32'h0 700h False 32 bits 0000_0000h Description PowerWell ResetSignal Always on count (AONC_CNT) 32 Bit Counter value 24.3.1.
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System Control Subsystem 24.3.1.61 Always on periodic timer (AONPT_CNT) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:0 RO/V/P 32'h0 708h False 32 bits 0000_0000h Description PowerWell ResetSignal Periodic Always On Timer (AONPT_CNT) 32 Bit Always On Timer Value 24.3.1.
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System Control Subsystem 24.3.1.
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System Control Subsystem 24.3.1.64 Always on periodic timer configuration register (AONPT_CFG) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default 714h False 32 bits 0000_0000h Bits Access Type Default Description PowerWell 31:0 RW/P 32'h0 Periodic always on time out configuration (AONPT_CFG) ResetSignal 0000h: Periodic Always On Counter Disabled.
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System Control Subsystem Bits Access Type Default 0 RW/P/L 1'h0 Description PowerWell ResetSignal Watchdog Speed Up (WDT_SPEED_UP) Debug mode allowing the watchdog time-out to be accelerated 0b : Watchdog Speed Up Disabled 1b : Watchdog Speed Up Enabled 24.3.1.
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System Control Subsystem 24.3.1.67 Pin Mux Pullup (PMUX_PULLUP) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:26 RO 6'h00 900h False 32 bits 00D0_0000h Description PowerWell ResetSignal RSVD (RSVD) Reserved 25:0 RW/P/L 26'h0D00000 Pin Mux Pullup Enable (PMUX_PU_EN) 0b: disable pull-up 1b: enables pullup(49kOhms typ) 24.3.1.
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System Control Subsystem 24.3.1.69 Pin Mux Input Enable (PMUX_IN_EN) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:26 RO 6'h00 920h False 32 bits 03FF_FFFFh Description PowerWell ResetSignal RSVD (RSVD) Reserved 25:0 RW/P/L 26'h3FFFFFF Pin mux input enable (PMUX_IN_EN) 0b: disable input pad 1b: enables input pad 24.3.1.70 Pin Mux Select (PMUX_SEL [0..
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System Control Subsystem Bits Access Type Default 25:24 RW/P/L 2'h0 Description PowerWell ResetSignal Pin Mux Select 12 (PMUX_SEL12) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2 11b: Select User Mode 3 23:22 RW/P/L 2'h0 Pin Mux Select 11 (PMUX_SEL11) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2 11b: Select User Mode 3 21:20 RW/P/L 2'h0 Pin Mux Select 10 (PMUX_SEL10) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2
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System Control Subsystem Bits Access Type Default 11:10 RW/P/L 2'h0 Description PowerWell ResetSignal Pin Mux Select 5 (PMUX_SEL5) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2 11b: Select User Mode 3 9:8 RW/P/L 2'h0 Pin Mux Select 4 (PMUX_SEL4) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2 11b: Select User Mode 3 7:6 RW/P/L 2'h0 Pin Mux Select 3 (PMUX_SEL3) 00b: Select User Mode 0 01b: Select User Mode 1 10b: Select User Mode 2 11b: Sele
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System Control Subsystem 24.3.1.71 Pin Mux Pullup Lock (PMUX_PULLUP_LOCK) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bit s Acces s Type Default 31: 1 RO 31'h0000_000 0 0 RW/1S 1'h0 94Ch False 32 bits 0000_0000h Description PowerWel l ResetSigna l RSVD (RSVD) Reserved Pin Mux Pullup 0 Enable Lock (PMUX_PU0_EN_LOCK ) pwr_rst_n 1b: Lock pull-up 24.3.1.
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System Control Subsystem 24.3.1.
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System Control Subsystem Bits Access Type Default 19 RW/1S 1'h0 Description PowerWell Pin Mux Select Lock 3 (PMUX_SEL3) ResetSignal pwr_rst_n 1b: Lock Pmux Select 18 RW/1S 1'h0 Pin Mux Select Lock 2 (PMUX_SEL2) pwr_rst_n 1b: Lock Pmux Select 17 RW/1S 1'h0 Pin Mux Select Lock 1 (PMUX_SEL1) pwr_rst_n 1b: Lock Pmux Select 16 RW/1S 1'h0 Pin Mux Select Lock 0 (PMUX_SEL0) pwr_rst_n 1b: Lock Pmux Select 15 RW/1S 1'h0 Pin Mux Select Lock 15 (PMUX_SELY15) pwr_rst_n 1b: Lock Pmux Select
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System Control Subsystem Bits Access Type Default 5 RW/1S 1'h0 Description PowerWell Pin Mux Select Lock 5 (PMUX_SELY5) ResetSignal pwr_rst_n 1b: Lock Pmux Select 4 RW/1S 1'h0 Pin Mux Select Lock 4 (PMUX_SELY4) pwr_rst_n 1b: Lock Pmux Select 3 RW/1S 1'h0 Pin Mux Select Lock 3 (PMUX_SELY3) pwr_rst_n 1b: Lock Pmux Select 2 RW/1S 1'h0 Pin Mux Select Lock 2 (PMUX_SELY2) pwr_rst_n 1b: Lock Pmux Select 1 RW/1S 1'h0 Pin Mux Select Lock 1 (PMUX_SELY1) pwr_rst_n 1b: Lock Pmux Select 0
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System Control Subsystem 24.3.1.75 Identification Register (ID) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:8 RO 24'h000000 1000h False 32 bits 0000_0010h Description PowerWell ResetSignal PowerWell ResetSignal RSVD (RSVD) Reserved 7:0 RO 8'h10 Major Revision ID (ID) Identifies SoC revision. 10h : Revision 1.0 24.3.1.
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System Control Subsystem 24.3.1.77 Flash Size Register (FS) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:16 RO 16'h0000 1008h False 32 bits 0000_0024h Description PowerWell ResetSignal PowerWell ResetSignal RSVD (RSVD) Reserved 15:0 RO 16'h0024 Flash Size Register (FS) Indicates Flash Size in KB 24.3.1.
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System Control Subsystem 24.3.1.79 Code OTP Size Register (COTPS) MEM Offset (00000000) Security_PolicyGroup IntelRsvd Size Default Bits Access Type Default 31:16 RO 16'h0000 1010h False 32 bits 0000_0008h Description PowerWell ResetSignal PowerWell ResetSignal RSVD (RSVD) Reserved 15:0 RO 16'h0008 Code OTP Size Register (COTPS) Indicates Code OTP Size in KB 24.3.1.
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AON Counters 25 AON Counters The SOC supports 2 Always On (AON) counters. The first counter is an always on free running counter running off the 32kHz RTC clock. The second is a periodic counter which allows a timer value to be loaded, and an interrupt to fire when the timer expires. 25.1 Features 25.1.1 AON Counter The following is a list of AON counters features: • • • • 25.1.
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AON Counters Before setting AONPT_RST register to 1, check if RTC OSC has attained lock and is running. This is achieved by checking for non-zero value of AON Counter, which freeruns on RTC clock if enabled. The counter can the reset to the value contained in (AONPT_CFG) by writing to 1 to (AONPT_RST). (AONPT_RST) is self-clearing however due to clock domain crossing of register value from the slow to the fast domain, it needs to be polled to ensure the reset has occurred. 1. 2. 3. 4. 5.