Network Card User Manual

32 MPCMM0001 Chassis Management Module Software Technical Product Specification
Built-In Self Test (BIST)
The BIST has been broken down into stages consisting of groups of tests that run at certain times
throughout the boot process. The following table shows the different BIST stages and the tests
associated with each stage:
Figure 1. BIST Flow Chart
Power Up/
Reset
RB image
and backup
RB image
checksum
Memory Test
FPGA,
DS1307, NIC
BlueCat
loaded (active
CMM)
BlueCat
Image
C
hecksu
m
Load backup
FPGA image
Jump to
run from
RB
Run from
backup
RB
Load FPGA
image
NOT (backup
FPGA image
pass and
FPGA image
fail)
backup FPGA
image pass
and FPGA
image fail
RB image pass
RB image fail
FPGA image
and backup
FPGA image
checksum
IPMB
Bus Test
Table 4. BIST Implementation
Boot-BIST Early-BIST Mid-BIST Late-BIST
RedBoot image
checksum
Strobe WDT to extend
timeout period
Extended memory test BlueCat image checksum
FPGA image checksum FPGA version check IPMB bus test
Base memory test DS1307 RTC test
Local PCI bus/NIC
presence test