Intel® Compute Module MFS5520VI Technical Product Specification Intel order number: E64311-005 Revision 1.
Revision History Intel® Compute Module MFS5520VI TPS Revision History Date February, 2009 Revision Number 1.0 Modifications Initial release. June, 2009 1.1 Updated the document. March, 2010 1.2 Updated the document. April, 2010 1.3 Updated the document. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Intel® Compute Module MFS5520VI TPS Table of Contents Table of Contents 1. Introduction .......................................................................................................................... 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Intel® Compute Module Use Disclaimer................................................................... 1 2. Product Overview.........................................
Table of Contents Intel® Compute Module MFS5520VI TPS 4.2 Power Connectors ................................................................................................. 23 4.3 I/O Connector Pin-out Definition ............................................................................ 24 4.3.1 VGA Connector...................................................................................................... 24 4.3.2 I/O Mezzanine Card Connector .........................................................
Intel® Compute Module MFS5520VI TPS List of Figures List of Figures Figure 1. Component and Connector Location Diagram .............................................................. 3 Figure 2. Intel® Compute Module MFS5520VI Front Panel Layout............................................... 4 Figure 3. Intel® Compute Module MFS5520VI – Hole and Component Positions ........................ 5 Figure 4. Intel® Compute Module MFS5520VI Functional Block Diagram .................................... 6 Figure 5.
List of Tables Intel® Compute Module MFS5520VI TPS List of Tables Table 1. Mixed Processor Configurations ..................................................................................... 8 Table 2. Mirroring DIMM Population Rules Variance across Nodes ........................................... 15 Table 3. Intel® Compute Module MFS5520VI PCI Bus Segment Characteristics....................... 18 Table 4. Video Modes ......................................................................................
Intel® Compute Module MFS5520VI TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Compute Module MFS5520VI. 1.
Product Overview 2. Intel® Compute Module MFS5520VI TPS Product Overview The Intel® Compute Module MFS5520VI is a monolithic printed circuit board with features that were designed to support the high-density compute module market. 2.1 Intel® Compute Module MFS5520VI Feature Set Feature Processors Description Support for one or two Intel® Xeon® Processor 5500 series or two Intel® Xeon® Processor 5600 series in FC-LGA 1366 Socket B package with up to 95 W Thermal Design Power (TDP). ® ® 4.8 GT/s, 5.
Intel® Compute Module MFS5520VI TPS 2.2 Product Overview Compute Module Layout 2.2.1 Connector and Component Locations The following figure shows the board layout of the Intel® Compute Module MFS5520VI. Each connector and major component is identified by a number or letter. A description of each identified item is provided below the figure.
Product Overview Intel® Compute Module MFS5520VI TPS A B C D E F G H I AF003120 A USB ports 0 and 1 F Hard Drive Activity LED B USB ports 2 and 3 G ID LED C Video H Power button D I/O Mezzanine NIC ports 1 and 2 LEDs I Power and Fault LEDs E NIC ports 1 and 2 LEDs Figure 2. Intel® Compute Module MFS5520VI Front Panel Layout 4 Intel order number: E64311-005 Revision 1.
Intel® Compute Module MFS5520VI TPS 253.74 169.85 Compute Module Mechanical Drawings 102.02 2.2.3 Product Overview 262.89 256.54 254.58 244.42 249.42 239.84 234.26 224.10 223.39 213.94 209.52 207.65 192.99 185.99 203.78 173.99 166.99 152.27 148.40 142.11 141.77 131.95 121.79 111.63 101.47 120.65 115.85 104.50 98.85 72.65 58.10 41.40 14.58 3.27 .000 396.24 357.34 300.35 248.92 185.93 138.84 AF003121 .000 10.16 101.10 6.35 Figure 3.
Functional Architecture 3. Intel® Compute Module MFS5520VI TPS Functional Architecture The architecture and design of the Intel® Compute Module MFS5520VI is based on the Intel® 5520 Chipset I/O Hub (IOH) and the Intel® 82801JR ICH10 RAID. The chipset is designed for systems based on the Intel® Xeon® Processor in FC-LGA 1366 socket B package with Intel® QuickPath Interconnect (Intel® QPI).
Intel® Compute Module MFS5520VI TPS 3.1 Functional Architecture Intel® Xeon® processor 3.1.1 Processor Support The Compute Module supports the following processors: One or two Intel® Xeon® Processor 5500 series with 4.8 GT/s, 5.86 GT/s or 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W. One or two Intel® Xeon® Processor 5600 series with a 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W.
Functional Architecture Intel® Compute Module MFS5520VI TPS Minor: The message is displayed on the screen or on the Error Manager screen. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The POST Error Pause option setting in the BIOS setup does not have any effect on this error. Table 1.
Intel® Compute Module MFS5520VI TPS Error Processor microcode missing 3.1.3 Severity Minor Functional Architecture System Action The BIOS detects the error condition and responds as follows: Logs the error. Does not disable the processor. Displays “8180: Processor 0x microcode update not found” message in the Error Manager or on the screen. The system continues to boot in a degraded state, regardless of the setting of POST Error Pause in the Setup.
Functional Architecture 3.1.6 Intel® Compute Module MFS5520VI TPS Unified Retention System Support The Compute Module complies with Intel’s Unified Retention System (URS) and the Unified Backplate Assembly. The Compute Module ships with a made-up assembly of Independent Loading Mechanism (ILM) and Unified Backplate at each processor socket. The URS retention transfers load to the Compute Module through the unified backplate assembly.
Intel® Compute Module MFS5520VI TPS 3.2 Functional Architecture Memory Subsystem Intel® QuickPath Memory Controller 3.2.1 The Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor 5600 series have an integrated memory controller, the Intel® QuickPath Memory Controller, in its package. The memory controller supports DDR3 1333/1066/800 ECC registered DIMMs (RDIMMs) and ECC unbuffered DIMMs (UDIMMs). Intel® Compute Module MFS5520VI Supported Memory 3.2.1.
Functional Architecture 3.2.3 Intel® Compute Module MFS5520VI TPS Memory Map and Population Rules The nomenclature for DIMM sockets implemented on the Intel® Compute Module MFS5520VI is detailed in the following figures. Channel A A1 A2 Processor Socket 1 Channel B Channel C B1 B2 C1 C2 Channel D D1 Processor Socket 2 Channel E Channel F D2 E1 E2 F1 F2 Figure 6.
Intel® Compute Module MFS5520VI TPS Functional Architecture The compute module Quick Reference Label DIMM slot identifiers provide information about the channel, and therefore the processor to which they belong. For example, DIMM_A1 is the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2. The memory slots associated with a given processor are unavailable if the given processor socket is not populated.
Functional Architecture Intel® Compute Module MFS5520VI TPS achieved across channels. Active channels hold the primary image and the other channels hold the secondary image of the system memory. The integrated memory controller in the Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor 5600 series processors alternates between both channels for read transactions. Write transactions are issued to both channels under normal circumstances.
Intel® Compute Module MFS5520VI TPS Functional Architecture socket 2 are mutually independent. As a result, if channel A and channel B have identical DIMM population and channel D and channel E have identical DIMM population, then mirroring is possible. For example, if the system is populated with six DIMMS {A1, B1, A2, B2, D1, E1}, channel mirroring is possible. Both the populations shown in the following table are valid. Table 2. Mirroring DIMM Population Rules Variance across Nodes A1 A2 P P 3.2.
Functional Architecture Intel® Compute Module MFS5520VI TPS The memory operational mode is configurable at the channel level. Two modes are supported: Independent Channel and Mirrored Channel. The memory slots of each DDR3 channel from the Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor 5600 series are populated on a farthest first fashion. This holds true even for the Independent Channel mode. Therefore, if A1 is empty, A2 cannot be populated or used.
Intel® Compute Module MFS5520VI TPS 3.3 Functional Architecture Intel® 5520 Chipset IOH The Intel® 5520 Chipset component is an I/O Hub (IOH.) The Intel® 5520 Chipset IOH provides a connection point between various I/O components and Intel processors through the Intel® QPI interface. The Intel® 5520 Chipset IOH is capable of interfacing with up to 36 PCI Express* lanes, which can be configured in various combinations of x4, x8, x16, and limited x2 and x1 devices.
Functional Architecture 3.4.1 Intel® Compute Module MFS5520VI TPS PCI Subsystem The primary I/O buses for the Intel® Compute Module MFS5520VI are PCI Express* Gen1 and PCI Express* Gen2 with six independent PCI bus segments. PCI Express* Gen1 and Gen2 are dual-simplex point-to point serial differential low-voltage interconnects. A PCI Express* topology can contain a host bridge and several endpoints (I/O devices). The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 and 5.
Intel® Compute Module MFS5520VI TPS Functional Architecture Four external connectors are located on the front of the compute module. One internal 2x5 header is provided, capable of supporting a low-profile USB solid state drive. Two ports are routed to the Integrated BMC to support rKVM. 3.
Functional Architecture Intel® Compute Module MFS5520VI TPS 2D Graphics Acceleration DDR2 graphics memory interface Up to 1600x1200 pixel resolution Figure 8. Integrated BMC Hardware 20 Intel order number: E64311-005 Revision 1.
Intel® Compute Module MFS5520VI TPS 3.5.1 Functional Architecture Floppy Disk Controller The Compute Module does not support a floppy disk controller interface. However, the compute module BIOS recognizes USB floppy devices. 3.5.2 Keyboard and Mouse Support The Compute Module does not support PS/2 interface keyboards and mice. However, the compute module BIOS recognizes USB specification-compliant keyboard and mice. 3.5.
Functional Architecture Intel® Compute Module MFS5520VI TPS The Intel® 82575EB device provides two standard IEEE 802.3 Ethernet interface through its SERDES interfaces. Each network interface controller (NIC) drives two LEDs located on the front panel. The LED indicates transmit / receive activity when blinking. 3.7.1 Direct Cache Access (DCA) Direct Cache Access (DCA) is a component of Intel® I/O Acceleration Technology 2 (Intel® I/OAT2).
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin-outs 4. Connector/Header Locations and Pin-outs 4.1 Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the compute module. The following table lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 5. Board Connector Matrix 4.
Connector/Header Locations and Pin-outs 4.3 4.3.1 Intel® Compute Module MFS5520VI TPS I/O Connector Pin-out Definition VGA Connector The following table details the pin-out definition of the VGA connector (J6K1). Table 7. VGA Connector Pin-out (J6A1) Pin 4.3.
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin-outs Table 8. 120-pin I/O Mezzanine Card Connector Pin-out Signal Name Revision 1.
Connector/Header Locations and Pin-outs Signal Name Intel® Compute Module MFS5520VI TPS GND 89 Pin Signal Name PCIe_1_D_TXP 90 Pin GND 91 PCIe_1_D_TXN 92 PCIe_1_D_RXP 93 GND 94 PCIe_1_D_RXN 95 GND 96 98 GND 97 Mezz_Present GND 99 Reset_N 100 Clk0_100M_PCIE_P 101 GND 102 Clk0_100M_PCIE_N 103 GND 104 GND 105 Rsvd 106 GND 107 Rsvd 108 Rsvd 109 GND 110 Rsvd 111 Rsvd 112 Rsvd 113 Rsvd 114 P12V 115 P12V 116 P12V 117 P12V 118 P12V 119 P12V 120 Tabl
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin-outs Signal Name PCIe_1_C_TXN Signal Description PCIe TX- of Lane C Link 1 Purpose Host connect 84 Connector Location PCIe_1_C_RXP PCIe RX+ of Lane C Link 1 Host connect 85 PCIe_1_C_RXN PCIe RX- of Lane C Link 1 Host connect 87 PCIe_1_D_TXP PCIe TX+ of Lane D Link 1 Host connect 90 PCIe_1_D_TXN PCIe TX- of Lane D Link 1 Host connect 92 PCIe_1_D_RXP PCIe RX+ of Lane D Link 1 Host connect 93 PCIe_1_D_RXN PCIe RX
Connector/Header Locations and Pin-outs Intel® Compute Module MFS5520VI TPS Table 10.
Intel® Compute Module MFS5520VI TPS Pin B4 Signal Name XE_P1_B_TXP Pin F4 Connector/Header Locations and Pin-outs Signal Name 12V (BL_PWR_ON) Pin J4 Signal Name GND B5 XE_P1_C_RXN F5 GND J5 reserved B6 XE_P1_C_TXP F6 XE_P2_B_TXN J6 GND B7 XE_P1_D_RXN F7 GND J7 reserved B8 XE_P1_D_TXP F8 XE_P2_A_TXN J8 GND C1 GND G1 SAS_P1_RXP K1 SMB_SDA_A C2 XE_P1_A_TXN G2 GND K2 FM_BL_SLOT_ID0 C3 GND G3 XE_P2_C_RXP K3 FM_BL_SLOT_ID3 C4 XE_P1_B_TXN G4 GND K4 FM_BL_SLOT_
Connector/Header Locations and Pin-outs Intel® Compute Module MFS5520VI TPS Table 13. External USB Connector Pin-out Pin 1 +5V Signal Name USB_PWR Description 2 USB_N Differential data line paired with DATAH0 3 USB_P (Differential data line paired with DATAL0 4 GND Ground One low-profile 2x5 connector (J9B7) on the compute module provides an option to support lowprofile Intel® Z-U130 Value Solid State Drive. The pin-out of the connector is detailed in the following table. Table 14.
Intel® Compute Module MFS5520VI TPS 5. Jumper Block Settings Jumper Block Settings The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “▼”. 5.
Jumper Block Settings Intel® Compute Module MFS5520VI TPS Table 15. Recovery Jumpers Jumper Name J9A5: BMC Force Update Pins 1-2 What happens at system reset … BMC Firmware Force Update Mode – Disabled (Default) 2-3 BMC Firmware Force Update Mode – Enabled J9A3: Password Clear 1-2 These pins should have a jumper in place for normal operation. (Default) 2-3 If these pins are jumpered, the administrator and user passwords are cleared immediately.
Intel® Compute Module MFS5520VI TPS Jumper Block Settings 4. Move jumper from the default operating position (pins 1-2) to the “Enabled” position (pins 2-3) 5. Close the compute module. 6. Reinstall and power up the compute module. 7. Perform Integrated BMC firmware update procedure. 8. Power down the compute module. 9. Remove the compute module from the server system. 10. Move jumper from the “Enabled” position (pins 2-3) to the “Disabled” position (pins 1-2). 11. Close the compute module. 12.
Product Regulatory Requirements Intel® Compute Module MFS5520VI TPS 6. Product Regulatory Requirements 6.1 Product Regulatory Requirements The Intel® Compute Module MFS5520VI is evaluated as part of the Intel® Modular Server System MFSYS25/MFSYS35, which requires meeting all applicable system component regulatory requirements. Refer to the Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification for a complete listing of all system and component regulatory requirements. 6.
Intel® Compute Module MFS5520VI TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. Mixed processor steppings are supported as long as they are listed in the processor specification updates published by Intel Corporation. However, the stepping of one processor cannot be greater than one stepping back of the other.
Appendix B: Integrated BMC Sensor Tables Intel® Compute Module MFS5520VI TPS Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event / reading-type table information.
Intel® Compute Module MFS5520VI TPS Appendix B: Integrated BMC Sensor Tables Fault LED This column indicates whether an assertion of an event lights the front panel fault LED. The Integrated BMC aggregates all fault sources (including outside sources such as the BIOS) such that the LED will be lit as long as any source indicates that a fault state exists. The Integrated BMC extinguishes the fault LED when all sources indicate no faults are present.
Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # Sensor Type Intel® Compute Module MFS5520VI TPS Event / Reading Type Event Offset Triggers Contrib.
Intel® Compute Module MFS5520VI TPS Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # Sensor Type Event / Reading Type Event Offset Triggers BB +5.0V 19h Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Processor Sensor Specific BB +5.0V STBY BB +12.
Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # CATERR 68h CPU Missing IOH Thermal Trip Hot Swap KVM Session SOL Session 69h 6Ah 70h 71h 72h Proc Max Therm 9Fh Mezz Card Present C0h Attention State 40 C1h Sensor Type Processor 07h Processor 07h Temperature 01h FRU State 2Ch Intel® Compute Module MFS5520VI TPS Event / Reading Type Digital Discrete 03h Digital Discrete 03h Digital Discrete 03h Sensor Specific 6Fh OEM OEM C0h 70h OEM OEM C0h 73h Temperature Thre
Intel® Compute Module MFS5520VI TPS Sensor Name HDD BP Present Drive 1,2 Sensor # C2h C3h, C4h Slot ID C5h BMC Reset E1h [MDR] E2h Appendix B: Integrated BMC Sensor Tables Sensor Type Event / Reading Type Event Offset Triggers D0h 71h 1: Status LED Active (fault) Drive Slot Digital Discrete 0: Device Absent 0Dh Drive Slot 0Dh 08h 1: Device Present Sensor Specific Contrib.
Appendix C: POST Error Messages and Handling Intel® Compute Module MFS5520VI TPS Appendix C: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
Intel® Compute Module MFS5520VI TPS Appendix C: POST Error Messages and Handling Error Code 8160 Error Message Processor 01 unable to apply microcode update Major Response 8161 Processor 02 unable to apply microcode update Major 8180 Processor 0x microcode update not found. Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure.
Appendix C: POST Error Messages and Handling Intel® Compute Module MFS5520VI TPS Error Code 856A Error Message DIMM_F1 Component encountered a Serial Presence Detection (SPD) fail error. Major Response 856B DIMM_F2 Component encountered a Serial Presence Detection (SPD) fail error. Major 85A0 DIMM_A1 Uncorrectable ECC error encountered. Major 85A1 DIMM_A2 Uncorrectable ECC error encountered. Major 85A2 DIMM_B1 Uncorrectable ECC error encountered.
Intel® Compute Module MFS5520VI TPS Appendix C: POST Error Messages and Handling Error Code 0xA001 Error Message TPM device missing or not responding. Minor Response 0xA002 TPM device failure. Minor 0xA003 TPM device failed self test. Minor 0xA022 Processor component encountered a mismatch error. Major 0xA027 Processor component encountered a low voltage error. Minor 0xA028 Processor component encountered a high voltage error. Minor 0xA421 PCI component encountered a SERR error.
Appendix D: Supported Intel® Modular Server System Intel® Compute Module MFS5520VI TPS Appendix D: Supported Intel® Modular Server System The Intel® Compute Module MFS5520VI is supported in the following chassis: Intel® Modular Server System MFSYS25 Intel® Modular Server System MFSYS35 This section provides a high-level pictorial overview of the Intel® Modular Server System MFSYS25. For more details, refer to the Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification (TPS).
Intel® Compute Module MFS5520VI TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) followed by alpha entries (for example, “AGP 4x”). Acronyms are followed by non-acronyms.
Glossary Intel® Compute Module MFS5520VI TPS Term Definition IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB MCH Memory Controller Hub MD2 Me
Intel® Compute Module MFS5520VI TPS Glossary Term SMBus System Management Bus Definition SMI Server Management Interrupt (SMI is the highest priority non-maskable interrupt) SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time coordinate VID Voltage Ide
Reference Documents Intel® Compute Module MFS5520VI TPS Reference Documents For additional information, refer to the Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification. 50 Intel order number: E64311-005 Revision 1.
