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Compute Module MFS5000SI

Technical Product Specification

Intel order number: E15154-007

Revision 1.4

June 2009

Enterprise Platforms and Services Division

Summary of content (50 pages)

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Intel® Compute Module MFS5000SI Technical Product Specification Intel order number: E15154-007 Revision 1.
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Revision History Intel® Compute Module MFS5000SI TPS Revision History Date July 2007 Revision Number 0.95 Modifications Initial release. August 2007 0.96 Updated September 2007 1.0 Updated February 2008 1.1 Updated November 2008 1.2 Updated May 2009 1.3 Updated June 2009 1.4 Updated supported memory configurations Disclaimers Information in this document is provided in connection with Intel® products.
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Intel® Compute Module MFS5000SI TPS Table of Contents Table of Contents 1. 2. 3. Introduction............................................................................................................................. 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Intel® Compute Module Use Disclaimer................................................................... 1 Product Overview..............................
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Table of Contents 5. 4.3.4 Serial Port Connector ............................................................................................ 24 4.3.5 USB 2.0 Connectors .............................................................................................. 25 Jumper Block Settings ............................................................................................................ 26 5.1 6. Intel® Compute Module MFS5000SI TPS Recovery Jumper Blocks ...................................
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Intel® Compute Module MFS5000SI TPS List of Figures List of Figures Figure 1. Component and Connector Location Diagram .............................................................. 3 Figure 2. Intel® Compute Module MFS5000SI Front Panel Layout............................................... 4 Figure 3. Intel® Compute Module MFS5000SI – Hole and Component Positions ........................ 5 Figure 4. Compute Module Functional Block Diagram .................................................................
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List of Tables Intel® Compute Module MFS5000SI TPS List of Tables Table 1. I2C Addresses for Memory Module SMB ........................................................................ 9 Table 2. Maximum 8-DIMM System Memory Configuration – x8 Single Rank ........................... 10 Table 3. Maximum 8-DIMM System Memory Configuration – x4 Dual Rank.............................. 10 Table 4. PCI Bus Segment Characteristics.................................................................................
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Intel® Compute Module MFS5000SI TPS 1. 0BIntroduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Compute Module MFS5000SI. The Intel® 5000 Series Chipsets Server Board Family Datasheet should also be referenced for more in-depth detail of various board subsystems, including chipset, BIOS, System Management, and System Management software. 1.
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1BProduct Overview 2. Intel® Compute Module MFS5000SI TPS Product Overview The Intel® Compute Module MFS5000SI is a monolithic printed circuit board with features that were designed to support the high-density compute module market. 2.
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Intel® Compute Module MFS5000SI TPS 2.2 1BProduct Overview Compute Module Layout 2.2.1 Connector and Component Locations The following figure shows the board layout of the Intel® Compute Module MFS5000SI. Each connector and major component is identified by a number or letter. A description of each identified item is provided below the figure.
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1BProduct Overview 2.2.2 Intel® Compute Module MFS5000SI TPS External I/O Connector Locations The following drawing shows the layout of the external I/O components for the Intel® Compute Module MFS5000SI. A USB ports 1 and 2 E Hard Drive Activity LED B Video F ID LED C I/O ports 1 and 2 G Power button D NIC ports 1 and 2 H Power and Fault LEDs Figure 2. Intel® Compute Module MFS5000SI Front Panel Layout 4 Intel order number: E15154-007 Revision 1.
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Intel® Compute Module MFS5000SI TPS 2.2.3 1BProduct Overview Compute Module Mechanical Drawings Figure 3. Intel® Compute Module MFS5000SI – Hole and Component Positions Revision 1.
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2BFunctional Architecture 3. Intel® Compute Module MFS5000SI TPS Functional Architecture The architecture and design of the Intel® Compute Module MFS5000SI is based on the Intel® 5000 Chipset Family. The chipset is designed for systems based on the Dual-Core and Quad-Core Intel® Xeon® processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz.
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Intel® Compute Module MFS5000SI TPS 3.1 2BFunctional Architecture Intel® 5000P Memory Controller Hub (MCH) This section describes the general functionality of the memory controller hub as it is implemented on this server board.
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2BFunctional Architecture 3.1.2.2 Intel® Compute Module MFS5000SI TPS Common Enabling Kit (CEK) Design Support The compute module complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The compute module ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the processor and the thermal interface material (TIM).
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Channel B Channel C Channel A Channel D H MC 1 M A A2 M I D M DIM M B1 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02299 Figure 6. Memory Layout To boot the system, the system BIOS on the server board uses a dedicated I2C bus to retrieve DIMM information needed to program the MCH memory registers. The following table provides the I2C addresses for each DIMM slot. Table 1.
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2BFunctional Architecture 3.1.3.2 Intel® Compute Module MFS5000SI TPS Supported and Nonsupported Memory Configurations The server board design supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory). Use of identical DIMMs with this server board is recommended. The following tables show the maximum memory configurations supported using the specified memory technology. Table 2.
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Supported and Validated configuration : Slot is populated Supported but not validated configuration : Slot is populated Slot is not populated Mirroring: Sparing: Y = Yes and indicates that configuration supports Memory Mirroring. Y(x) = Yes and indicates that configuration supports Memory Sparing.
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2BFunctional Architecture Intel® Compute Module MFS5000SI TPS Channel B Channel C Channel A Channel D H MC 1 M A A2 M I D M DIM M B1 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02300 Figure 7. Recommended Minimum Two-DIMM Memory Configuration Note: The server board supports single DIMM mode operation. Intel only validates and supports this configuration with a single 512MB x8 FBDIMM installed in DIMM slot A1. 3.1.3.
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Channel B Channel C Channel A Channel D H MC 1 M A A2 M I D M DIM M B1 2 DIM M B 1 DIM M C 2 DIM M C 1 DIM M D 2 DIM M D DIM Branch 0 Branch 1 TP02301 Figure 8. Recommended Four-DIMM Configuration Functionally, DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1. However, your system will not achieve equivalent performance.
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2BFunctional Architecture 3.1.3.4.2.1 Intel® Compute Module MFS5000SI TPS Single Branch Mode Sparing Slot 2 DIMM_A2 DIMM_B2 DIMM_C2 DIMM_D2 Slot 1 DIMM_A1 DIMM_B1 DIMM_C1 DIMM_D1 Channel B Channel C Channel D Channel A Branch 0 Branch 1 Intel® 5000P/5000X Memory Controller Hub Figure 9. Single Branch Mode Sparing DIMM Configuration DIMM_A1 and DIMM_B1 must be identical in organization, size and speed. DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Note: Use of identical memory is recommended with the Intel® Compute Module MFS5000SI. Mixing memory type, size, speed, rank and/or vendors is not validated and is not supported with this product. Refer to section 3.1.3.2 for supported and nonsupported memory features and configuration information. Revision 1.
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2BFunctional Architecture 3.2 Intel® Compute Module MFS5000SI TPS Intel® 6321ESB I/O Controller Hub The Intel® 6321ESB I/O Controller Hub is a multi-function device that provides four distinct functions: an IO Controller, a PCI-X Bridge, a Gb Ethernet Controller, and an Integrated Baseboard Management Controller (BMC). Each function within the Intel® 6321ESB I/O Controller Hub has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller.
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Intel® Compute Module MFS5000SI TPS PCI Bus Segment PE6, PE7 BNB PCI Express* Ports 6,7 3.2.1.1 Voltage 3.3V Width x8 2BFunctional Architecture Speed 20 Gb/S Type On-board Device Support PCI This interface is not used in the Intel® Express* Compute Module MFS5000SI design. PCI32: 32-bit, 33-MHz PCI Bus Segment All 32-bit, 33-MHz PCI I/O is directed through the Intel® 6321ESB I/O Controller Hub.
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2BFunctional Architecture 3.2.4 Intel® Compute Module MFS5000SI TPS USB 2.0 Support The USB controller functionality integrated into the Intel® 6321ESB I/O Controller Hub provides the server board with the interface for up to eight USB 2.0 ports. Two external connectors are located on the front edge of the server board. These two ports are the only ports of the Intel® 6321ESB I/O Controller Hub that are used in the compute module design. 3.
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Intel® Compute Module MFS5000SI TPS 3.4 2BFunctional Architecture Network Interface Controller (NIC) Network interface support is provided from the built-in Dual GbE MAC features of the Intel® 6321ESB I/O Controller Hub. These interfaces are routed over the midplane board to the Ethernet switch module in the rear of the system. These interfaces are used in SERDES mode and do not require a Physical Layer Transceiver (PHY).
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2BFunctional Architecture Intel® Compute Module MFS5000SI TPS Table 6. Serial Header Pin-out 3.5.1.2 Pin 1 Signal Name DCD 2 DSR 3 RX 4 RTS 5 TX 6 CTS 7 DTR 8 RI 9 GND Serial Port Header Pin-out Floppy Disk Controller The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS does recognize USB floppy devices. 3.5.1.
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Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs 4. Connector / Header Locations and Pin-outs 4.1 Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. Table 7 lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 7. Board Connector Matrix Connector Power Connector 4.
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3BConnector / Header Locations and Pin-outs 4.3 Intel® Compute Module MFS5000SI TPS I/O Connector Pin-out Definition 4.3.1 VGA Connector The following table details the pin-out definition of the VGA connector (J6K1). Table 9. VGA Connector Pin-out (J6A1) Pin 4.3.
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Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs A10 GND E10 SMB_SCL I10 P12V B1 PE4_MCH_RXN_C0 F1 GND J1 XE_P2_D_RXN B2 PE4_MCH_TXP_C0 F2 PE5_MCH_TXN_C0 J2 GND B3 PE4_MCH_RXN_C1 F3 GND J3 XE_P2_C_RXN B4 PE4_MCH_TXP_C1 F4 PE5_MCH_TXN_C1 J4 GND B5 PE4_MCH_RXN_C2 F5 GND J5 XE_P2_B_RXN B6 PE4_MCH_TXP_C2 F6 PE5_MCH_TXN_C2 J6 GND B7 PE4_MCH_RXN_C3 F7 GND J7 XE_P2_A_RXN B8 PE4_MCH_TXP_C3 F8 PE5_MCH_TXN_C3 J8 GND B9 CLK_100M_PC
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3BConnector / Header Locations and Pin-outs Intel® Compute Module MFS5000SI TPS A6 GND E6 XE_P2_B_TXP I6 SAS_P2_TXN A7 XE_P1_D_RXP E7 XE_P2_A_RXN I7 GND A8 GND E8 XE_P2_A_TXP I8 Fm_bl_slot_id5 B1 XE_P1_A_RXN F1 GND J1 SMB_SCL_A B2 XE_P1_A_TXP F2 XE_P2_D_TXN J2 GND B3 XE_P1_B_RXN F3 GND J3 FM_BL_SLOT_ID2 B4 XE_P1_B_TXP F4 12V (BL_PWR_ON) J4 GND B5 XE_P1_C_RXN F5 GND J5 reserved B6 XE_P1_C_TXP F6 XE_P2_B_TXN J6 GND B7 XE_P1_D_RXN F7 GND J7 reserved
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Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs Table 6 for the pin-out of the serial header. Table 12. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) Pin 4.3.
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4BJumper Block Settings 5. Intel® Compute Module MFS5000SI TPS Jumper Block Settings The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “▼”. 5.
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Intel® Compute Module MFS5000SI TPS 4BJumper Block Settings Table 14. Recovery Jumpers Jumper Name J7A1: BMC Force Update Pins 1-2 What happens at system reset … BMC Firmware Force Update Mode – Enabled 2-3 BMC Firmware Force Update Mode – Disabled (Default) J4A1: Password Clear 1-2 These pins should have a jumper in place for normal system operation. (Default) 2-3 If these pins are jumpered, the administrator and user passwords are cleared immediately.
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4BJumper Block Settings 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
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Intel® Compute Module MFS5000SI TPS 6. 6.1 5BProduct Regulatory Requirements Product Regulatory Requirements Product Regulatory Requirements ® The Intel Compute Module MFS5000SI is evaluated as part of the Intel® Modular Server System MFSYS25/MFSYS35, which requires meeting all applicable system component regulatory requirements. Refer to the Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification for a complete listing of all system and component regulatory requirements. 6.
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Appendix A: Integration and Usage Tips Intel® Compute Module MFS5000SI TPS Appendix A: Integration and Usage Tips 30 When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. Mixed processor steppings is supported. However, the stepping of one processor cannot be greater than one stepping back of the other. Processors must be installed in order.
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Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Appendix B: BMC Sensor Tables Table 15 lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event / reading-type table information. Sensor Type The Sensor Type references the values enumerated in the Sensor Type Codes table in the IPMI Specification.
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Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Sensor Rearm The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. The following abbreviations are used in the column: ‘A’: Auto rearm ‘M’: Manual rearm Readable Some sensors are used simply to generate events into the System Event Log. The Watchdog timer sensor is one example.
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Intel® Compute Module MFS5000SI TPS Name # Sensor Type Event / Reading Type State 22h BB Vtt 10h Voltage Thresh. 01h BB +1.5V AUX 11h Voltage Thresh. 01h BB +1.5V 12h BB +1.8V BB +3.3V 13h 14h BB +3.3V STB 15h BB +1.5V ESB 16h BB +5V 17h BB +12V AUX 18h BB 0.9V 19h BB Vbat (SIO) Revision 1.4 1Ah Voltage Voltage Voltage Voltage Voltage Voltage Voltage Voltage Voltage Thresh. 01h Thresh. 01h Thresh. 01h Thresh. 01h Thresh. 01h Thresh. 01h Thresh. 01h Thresh.
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Appendix B: Sensor Tables Name # Sensor Type Intel® Compute Module MFS5000SI TPS Event / Reading Type Event Offset Triggers 1: Inactive Hot Swap 20h Hot Swap 2Ch Sensor Specific 6Fh 2: Activation Required 3: Activation In Progress 4: Active 5: Deactivation Required 6: Deactivation in Progress 0: Pending 1: Established KVM Session 21h OEM OEM C0h 70h 2: Ended Normally 3: Ticket Expiration 4: Lost Heartbeat 5: Forcibly Terminated 6: Unknown Ticket Status LED Read? Rearm Standby None None
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Intel® Compute Module MFS5000SI TPS Sensor Type Event / Reading Type Appendix B: Sensor Tables Name # Processor 1,2 Thermal Ctrl % 9Ah, 9Bh Temp. 01h Thresh. 01h Upper Critical Processor 1,2 VRD Hot 9Ch, 9Dh Temp. 01h Digital Discrete 05h Proc Max Thermal Margin 9Fh Temp Thresh.
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Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Table 16. Analog Sensor Thresholds Name # Sensor Type Lower Critical Lower NonCritical Upper NonCritical Upper Critical BB Vtt 10h Voltage 1.90V N/A N/A 1.5V BB +1.5V AUX 11h Voltage 1.33V N/A N/A 1.65V BB +1.5V 12h Voltage 1.33V N/A N/A 1.65V BB +1.8V 13h Voltage 1.67V N/A N/A 1.94V BB +3.3V 14h Voltage 2.97V N/A N/A 3.62V BB +3.3V STB 15h Voltage 2.97V N/A N/A 3.62V BB +1.
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Intel® Compute Module MFS5000SI TPS Appendix C: POST Error Messages and Handling Appendix C: POST Error Messages and Handling Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Appendix C: POST Error Messages and Handling Intel® Compute Module MFS5000SI TPS Error Code 8305 Hot swap controller failed Error Message Major Response 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory Component could not be configured in the selected RAS mode. Major 8510 System supports a maximum of 16 GB of main memory.
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Intel® Compute Module MFS5000SI TPS Appendix C: POST Error Messages and Handling Error Code 92A3 Error Message Serial port component was not detected. Major Response 92A9 Serial port component encountered a resource conflict error. Major 0xA000 TPM device not detected. Minor 0xA001 TPM device missing or not responding. Minor 0xA002 TPM device failure Minor 0xA003 TPM device failed self test.
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Appendix D: Supported Intel® Server Chassis Intel® Compute Module MFS5000SI TPS Appendix D: Supported Intel® Modular Server System The Intel® Compute Module MFS5000SI is supported in the following chassis: Intel® Modular Server System MFSYS25 Intel® Modular Server System MFSYS35 This section provides a high-level descriptive overview of each chassis. For more details, refer to the Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification (TPS).
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Intel® Compute Module MFS5000SI TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) followed by alpha entries (for example, “AGP 4x”). Acronyms are followed by non-acronyms.
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Glossary Intel® Compute Module MFS5000SI TPS Term Definition IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB MCH Memory Controller Hub MD2 Me
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Intel® Compute Module MFS5000SI TPS Term Glossary Definition SIO Server Input/Output SMBus System Management Bus SMI Server Management Interrupt (SMI is the highest priority non-maskable interrupt) SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time c
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Reference Documents Intel® Compute Module MFS5000SI TPS Reference Documents See the following documents for additional information: 44 Intel® 5000 Series Chipsets Server Board Family Datasheet Intel® 5000P Memory Controller Hub External Design Specification Intel® Enterprise South Bridge 2 (ESB2) External Design Specification Intel® Modular Server System MFSYS25/MFSYS35 Technical Product Specification Intel order number: E15154-007 Revision 1.