Datasheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet 99
Features
7.4.3.3.2 RES2: Reserved 2
These locations are reserved. Writes to this register have no effect.
7.4.3.3.3 FSB: Front Side Bus Speed
This location contains the front side bus frequency information. Systems may need to
read this offset to decide if all installed processors support the same front side bus
speed. Because the Intel NetBurst microarchitecture bus is described as a 4X data bus,
the frequency given in this field is currently 667 MHz or 800 MHz. The data provided is
the speed, rounded to a whole number, and reflected in hex. Writes to this register
have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series supports a 667 or 800 MHz
front side bus. Therefore, offset 1A - 1Bh has a value of 029Bh or 0320h.
7.4.3.3.4 MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are MSB aligned where 00b equates to single-
processor operation, 01b is a dual-processor operation, and 11b represents multi-
processor operation. The Dual-Core Intel Xeon processor 7100 series is an MP
processor. The remaining six bits in this field are reserved for the future use. Writes to
this register have no effect.
Example: An MP processor will use C0h at offset 1Ch.
Offset: 18h-19h
Bit Description
15:0 RESERVED 2
0000h-FFFFh: Reserved
Offset: 1Ah-1Bh
Bit Description
15:0 Front Side Bus Speed
0000h-029Ah: Reserved
029Bh: 667 MHz
029Ch-031Fh: Reserved
0320h: 800 Mhz
0321h-FFFFh: Reserved
Offset: 1Ch
Bit Description
7:6 Multiprocessor Support
UP, DP or MP indictor
00b: UP
01b: DP
10b: Reserved
11b: MP
5:0 RESERVED
000000b-111111b: Reserved