Datasheet

Features

98 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

7.4.3.2.3 PDCKS: Processor Data Checksum

This location provides the checksum of the Processor Data Section. Writes to this

7.4.3.3 Processor Core Data

This section contains core silicon-related data.

7.4.3.3.1 CPUID: CPUID

This location contains the CPUID, Processor Type, Family, Model and Stepping. The

CPUID field is a copy of the results in EAX[13:0] from Function 1 of the CPUID

instruction. The MSB is at location 16h, the LSB is at location 17h. Writes to this

Example: If the CPUID of a processor is 0F68h, then the value programmed into offset

16 - 17h of the PIROM is 3DA0h.

Note: The field is not aligned on a byte boundary since the first two bits of the offset are

reserved. Thus, the data must be shifted right by two in order to obtain the same

results.

Note: The first two bits of the PIROM are reserved, as highlighted in the example below.

CPUID instruction results 0000 1111 0110 1000 (0F68h)

PIROM content 0011 1101 1010 0000 (3DA0h)

Offset: 15h

Bit Description

7:0 Processor Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

Offset: 16h-17h

Bit Description

15:14 Processor Type

00b-11b: Processor Type

13:10 Processor Family

00h-0Fh: Processor Family

9:6 Processor Model

00h-0Fh: Processor Model

5:2 Processor Stepping

00h-0Fh: Processor Stepping

1:0 Reserved

00b-11b: Reserved