Datasheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet 69
Signal Definitions
INIT# I INIT# (Initialization), when asserted, resets integer registers inside all
processors without affecting their internal caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor front side bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then
the processor executes its Built-in Self-Test (BIST).
LINT0/INTR
LINT1/NMI
I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front
side bus agents. When the APIC functionality is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI,
a nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are
asynchronous.
These signals must be software configured via BIOS programming of the APIC
register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is
enabled by default after Reset, operation of these pins as LINT[1:0] is the
default configuration.
LOCK# I/O LOCK# indicates to the system that a set of transactions must occur atomically.
This signal must connect the appropriate pins of all processor front side bus
agents. For a locked sequence of transactions, LOCK# is asserted from the
beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor front side bus, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the processor front side bus
throughout the bus locked operation and ensure the atomicity of lock.
MCERR# I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
or a bus protocol violation. It may be driven by all processor front side bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined as follows:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32
Intel
®
Software Developer’s Manual, Volume 3: System Programming Guide or
the BIOS Writer’s Guide which includes the Dual-Core Intel® Xeon® Processor
7100 Series processor.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is activated
on specific clock edges and sampled on specific clock edges.
ODTEN I ODTEN (On-die termination enable) should be connected to V
TT
through a
resistor to enable on-die termination for end bus agents. For middle bus
agents, pull this signal down via a resistor to ground to disable on-die
termination. Whenever ODTEN is high, on-die termination will be active,
regardless of other states of the bus.
OOD# I OOD# allows data delivery to occur subsequent to IDS# assertion during the
Deferred Phase.
PROCHOT# O The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6.2.4 for more details.
PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all Dual-Core Intel Xeon processor 7100 series clocks and
power supplies are stable and within their specifications. “Clean” implies that
the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high
state. PWRGOOD can be driven inactive at any time, but clocks and power
must again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to
protect internal circuits against voltage sequencing issues. It should be driven
high throughout boundary scan operation.
Table 5-1. Signal Definitions (Sheet 5 of 8)
Name Type Description