Datasheet

Signal Definitions
68 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
DEP[7:0]# I/O The DEP[7:0]# (data bus ECC protection) signals provide optional ECC
protection for the data bus. They are driven by the agent responsible for
driving D[63:0]#, and, if ECC is implemented, must connect the appropriate
pins of all bus agents which use them.
Furthermore, the DBI# pins determine the polarity of the ECC signals. Each
pair of 2 ECC signals corresponds to one DBI# signal. When the DBI# signal is
active, the corresponding ECC pair is inverted and therefore sampled active
high.
DP[3:0]# I/O DP[3:0]# (Data Parity) provide optional parity protection for the data bus.
They are driven by the agent responsible for driving D[63:0]#, and, if parity is
implemented, must connect the appropriate pins of all bus agents which use
them.
DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor front side bus agents.
DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-
type floating-point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event waiting
for service. The assertion of FERR#/PBE# indicates that the processor should
be returned to the Normal state. For additional information on the pending
break event functionality, including the identification of support of the feature
and enable/disable information, refer to Vol 3 of the Intel
®
Architecture
Software Developer’s Manual and the Intel
®
Processor Identification and the
CPUID Instruction application note.
FORCEPR# I This input can be used to force activation of the Thermal Control Circuit.
GTLREF[3:0] I GTLREF determines the signal reference level for AGTL+ input pins. GTLREF is
used by the AGTL+ receivers to determine if a signal is an electrical 0 or an
electrical 1. Please refer to Tab l e 2- 2 3 for further details.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any front side bus agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together, every other common clock.
Since multiple agents may deliver snoop results at the same time, HIT# and
HITM# are wire-OR signals which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wire-OR glitches associated
with simultaneous edge transitions driven by multiple drivers, HIT# and HITM#
are activated on specific clock edges and sampled on specific clock edges.
ID[7:0]# I ID[7:0]# are the Transaction ID signals. They are driven during the Deferred
Phase by the deferring agent.
IDS# I IDS# is the ID Strobe signal. It is asserted to begin the Deferred Phase.
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor front side bus. This transaction may optionally be converted
to an external error signal (e.g., NMI) by system core logic. The processor will
keep IERR# asserted until the assertion of RESET#.
IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid a 6 clks before the I/O
write’s response.
Table 5-1. Signal Definitions (Sheet 4 of 8)
Name Type Description