Datasheet

Electrical Specifications
40 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
2.11 AGTL+ Front Side Bus Specifications
Routing topology recommendations are in the appropriate platform design guide.
Termination resistors are not required for most AGTL+ signals because they are
integrated into the processor silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s
voltage with a reference voltage called GTLREF.
Tab l e 2-2 3 lists the GTLREF specifications. GTLREF should be generated on the system
board using high-precision voltage divider circuits. For more details on platform design,
see the appropriate platform design guide.
Notes:
1. The tolerances for this specification have been stated generically to enable system designers to calculate
the minimum values across the range of V
TT
.
2. GTLREF is generated from V
TT
on the baseboard by a voltage divider of 1% resistors.
3. R
TT
is the on-die termination resistance measured at V
TT
/2 of the AGTL+ output driver.
4. R
L
is the on-die termination resistance for improved noise margin and signal integrity.
5. The COMP0 resistor is provided by the baseboard with 1% resistors. See the appropriate platform design
guide for implementation details.
6. The V
TT
referred to in these specifications refers to instantaneous V
TT
.
§
Table 2-23. AGTL+ Bus Voltage Definitions
Symbol Parameter Min Typ Max Units Notes
GTLREF Bus Reference
Voltage
0.98 * (0.63 *
V
TT
)
0.63 * V
TT
1.02 * (0.63 *
V
TT
)
V1,2,6
R
TT
Termination
Resistance (pull-up)
45 50 55 Ω 3
R
L
Termination
Resistance (pull-
down)
360 450 540 Ω 4
COMP0 COMP Resistance 49.4 49.9 50.4 Ω 5