Datasheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet 39
Electrical Specifications
Notes:
1. All outputs are open-drain.
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
4. The V
TT
referred to in these specifications refers to instantaneous V
TT
.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6. Leakage to V
SS
with pin held at V
TT
7. Leakage to V
TT
with pin held at 300 mV.
Notes:
1. These parameters are based on design characterization and are not tested.
2. All DC specifications for the SMBus signal group are measured at the processor pins.
3. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
Table 2-21. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
Symbol Parameter Min Max Unit Notes
V
IL Input Low Voltage 0 GTLREF - (10% * V
TT
)V 2
V
IH Input High Voltage GTLREF + (10% * V
TT
)V
TT
V3,4
V
IL A20M#, SMI#, IGNNE#
Input Low Voltage
00.4 * V
TT
V2
V
IH A20M#, SMI#, IGNNE#
Input High Voltage
0.6 * V
TT
V
TT
V3,4
V
OH Output High Voltage V
TT
V1,4
I
OL Output Low Current 50 mA 5
I
LI Input Leakage Current N/A ± 200 µA 6
I
LO Output Leakage Current ± 200 µA 7
Ron Buffer On Resistance 8 12 Ω
Table 2-22. SMBus Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1,2
V
IL
Input Low Voltage -0.30 0.30 * SM_VCC V
V
IH
Input High Voltage 0.70 * SM_VCC 3.465 V
V
OL
Output Low Voltage 0 0.400 V
I
OL
Output Low Current N/A 3.0 mA
I
LI
Input Leakage Current N/A ± 10 µA
I
LO
Output Leakage Current N/A ± 10 µA
C
SMB
SMBus Pin Capacitance 15.0 pF 3