Datasheet

Electrical Specifications
36 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Notes:
1. V
OS_CACHE
is measured overshoot voltage.
2. T
OS_CACHE
is measured time duration above Vcache_max.
2.10.4 Die Voltage Validation
Overshoot events from application testing on the processor must meet the
specifications in Ta b le 2-1 4 when measured across the V
CCSENSE
and V
SSSENSE
pins and
Tab l e 2-1 5 when measured across the V
CC_CACHE_SENSE
and V
SS_CACHE_SENSE
pins.
Overshoot events that are < 10 ns in duration may be ignored. These measurements of
processor die level overshoot should be taken with a 100 MHz bandwidth limited
oscilloscope.
2.10.5 Clock, Miscellaneous and AGTL+ Specifications
Figure 2-8. V
CACHE
Overshoot Example Waveform
Vcache Overshoot Example Waveform
Time (10 µs per division)
Vcache (10 mV per division)
V
OS
_
cache
TOS
_
cache
Vcache_max prior to
unloading transient
Vcache_max after
unloading transient
Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Unit Notes
V
L Input Low Voltage -0.150 0.000 N/A V
V
H Input High Voltage 0.660 0.700 0.850 V
V
CROSS(abs) Absolute Crossing
Point
0.250 N/A 0.550 V 1,7
V
CROSS(rel) Relative Crossing
Point
0.250 + 0.5*
(V
Havg
- 0.700)
N/A 0.550 + 0.5*
(V
Havg
- 0.700)
V2,7,8
Δ V
CROSS Range of Crossing
Point
N/A N/A 0.140 V
V
OV Overshoot N/A N/A + 0.300 V 3