Datasheet

Electrical Specifications
28 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
2.10 Processor DC Specifications
The following notes apply:
• The processor DC specifications in this section are defined at the processor core
silicon and not at the package pins unless noted otherwise.
• The notes associated with each parameter are part of the specification for that
parameter.
• Unless otherwise noted, all specifications in the tables apply to all frequencies and
cache sizes.
• Unless otherwise noted, all the specifications in the tables are based on estimates
and simulations. These specifications will be updated with characterized data from
silicon measurements at a later date.
See Section 5 for the pin signal definitions. Most of the signals on the processor front
side bus are in the AGTL+ signal group. The DC specifications for these signals are
listed in Tab l e 2-1 9.
Tab l e 2-1 0 through Tabl e 2-2 2 list the DC specifications for the Dual-Core Intel®
Xeon® Processor 7100 Series processor and are valid only while meeting specifications
for case temperature, clock frequency, and input voltages.
2.10.1 Flexible Motherboard (FMB) Guidelines
The FMB guidelines are estimates of the maximum values that the Dual-Core Intel Xeon
processor 7100 series processor will have over certain time periods. The values are
only estimates as actual specifications for future processors may differ. The Dual-Core
Intel Xeon processor 7100 series may or may not have specifications equal to the FMB
value in the foreseeable future. System designers should meet the FMB values to
ensure that their systems will be compatible with future releases of the Dual-Core Intel
Xeon processor 7100 series.
Table 2-10. Voltage and Current Specifications (Sheet 1 of 2)
Symbol Parameter
Core
Freq
Min Typ Max VID Unit Notes
VID Range V
CC
for processor core All freq Refer to Ta bl e 2 -1 1 1.1000 -
1.3500
V1,2,3,
4,5,7
VID Transition VID step size during
transition
All freq. ± 12.5 mV 18
Total allowable DC load line
shift from VID steps
All freq. 450 mV 19
CVID Range V
CC
for processor L3 cache All freq. Refer to Tab le 2 - 12 or Ta b l e 2- 13 1.1000 -
1.3500
V17
V
TT
FSB termination voltage
(DC specification)
All freq. 1.176 1.20 1.224 V 11,12,
13
V
TT
FSB termination voltage
(AC specification)
All freq. 1.140 1.20 1.260 V 11,12,
13,14
SM_VCC SMBus supply voltage All freq. 3.135 3.300 3.465 V 13
I
CC
I
CC
for processor core All freq 135 A 7,10
I
CC_TDC
Core Thermal Design
Current (TDC)
All freq 115 A 20
I
CACHE
I
CC
for processor L3 cache All freq 40 A