Datasheet

Electrical Specifications
20 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
2.1.3 Phase Lock Loop (PLL) Power and Filter
V
CCA
, V
CCIOPLL
, and V
CCA_CACHE
are power sources required by the PLL clock generators
on the Dual-Core Intel Xeon processor 7100 series. These are analog PLLs and they
require low noise power supplies for minimum jitter. These supplies must be low pass
filtered from V
TT
.
The AC low-pass requirements, with input at V
TT
, are as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-2. For recommendations on
implementing the filter, refer to the appropriate platform design guide.
Notes:
1. Diagram not to scale.
2. No specification for frequencies beyond f
core
(core frequency).
Table 2-3. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1 BSEL0 Function
0 0 RESERVED
0 1 RESERVED
1 0 200 MHz
1 1 166 MHz
Figure 2-2. Phase Lock Loop (PLL) Filter Requirements
0 dB
-28 dB
-34 dB
0.2 dB
forbidden
zone
-0.5 dB
forbidden
zone
1 MHz 66 MHz
f
core
f
peak1 HzDC
passband
high frequency
band