Datasheet

Features
116 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
7.4.9 SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the
SMBus when a fault condition exists. The fault conditions consist of:
1. a processor thermal diode value measurement that exceeds a user-defined high or
low threshold programmed into the Command Register; or
2. disconnection of the processor thermal diode from the thermal sensor.
The interrupt can be enabled and disabled via the thermal sensor Configuration
Register and is delivered to the system board via the SM_ALERT# open drain output.
Once latched, the SM_ALERT# should only
be cleared by reading the Alert Response
byte from the Alert Response Address of the thermal sensor. The Alert Response
Address is a special slave address shown in Tab l e 7-1 2. The SM_ALERT# will be cleared
once the SMBus master device reads the slave ARA unless the fault condition persists.
Reading the Status Register or setting the mask bit within the Configuration Register
does not clear the interrupt.
§
6 RESERVED RESERVED Reserved for future use.
5:4 Channel Selector 00 These bits are used to select the temperature
measurement channels.
00 = Round robin
01 = Local Temperature
10 = Processor Core 1 Temperature
11 = Processor Core 2 Temperature
Default = 00. Always set these bits to 00
3:0 Conversion Rates 1000 These bits determine how often the temperature sensor
measures each temperature channel.
Bit encoding = Conversions / sec
0000 = 0.0625
0001 = 0.125
0010 = 0.25
0011 = 0.5
0100 = 1
0101 = 2
0110 = 4
0111 = 8
1000 = 16 = default
1001 = 32
1010 = Continuous Measurements
Table 7-18. SMBus Thermal Sensor Conversion Rate Register
Bit Name Reset State Function