Datasheet

Features
104 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Example: The A-0 and A-1 steppings of the Dual-Core Intel Xeon processor 7100
series utilizes the first revision package (FC-mPGA4). Thus, at offset 32-35h, the data
is a space followed by 1.0. In hex, this would be 20, 31, 2E, 30. The B-0 stepping of the
Dual-Core Intel Xeon processor 7100 series utilizes the second revision package
(FC-mPGA6). Thus, at offset 32-35h, the data is a space followed by 2.0. In hex, this
would be 20, 32, 2E, 30.
7.4.3.5.2 RES5: Reserved 5
This location is reserved. Writes to this register have no effect.
7.4.3.5.3 PKDCKS: Package Data Checksum
This location provides the checksum of the Package Data Section. Writes to this register
have no effect.
7.4.3.6 Part Number Data
This section provides traceability. There are 208 available bytes in this section for
future use.
Offset: 32h-35h
Bit Description
31:24 Character 4
ASCII character or 20h
00h-0FFh: ASCII character
23:16 Character 3
ASCII character
00h-0FFh: ASCII character
15:8 Character 2
ASCII character
00h-0FFh: ASCII character
7:0 Character 1
ASCII character
00h-0FFh: ASCII character
Offset: 36h
Bit Description
7:0 RESERVED 5
00h-FFh: Reserved
Offset: 37h
Bit Description
7:0 Package Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value