Datasheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet 103
Features
7.4.3.4.5 MINCV: Minimum Cache Voltage
This location contains the minimum Cache voltage. This field, rounded to the next
thousandth, is in mV and is reflected in hex. The minimum V
CACHE
reflected in this field
is the minimum allowable voltage assuming the FMB maximum current draw for two
processors. Writes to this register have no effect.
Note: The minimum core voltage value in offset 2D - 2Eh is a single value that assumes the
FMB maximum current draw for two processors. Refer to Tab l e 2 -1 0 and Ta bl e 2 - 12 for
the minimum cache voltage specifications based on actual real-time current draw.
Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is
0.802 V = 1.100 V (Min CVID) - 0.298 V (Voltage Offset at maximum current). Offset
2D - 2Eh would contain 0322h (0802 decimal).
7.4.3.4.6 RES4: Reserved 4
These locations are reserved. Writes to this register have no effect.
7.4.3.4.7 CDCKS: Cache Data Checksum
This location provides the checksum of the Cache Data Section. Writes to this register
have no effect.
7.4.3.5 Package Data
This section provides package revision information.
7.4.3.5.1 PREV: Package Revision
This location tracks the highest level package revision. It is provided in ASCII format of
four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,
2.0, etc. If this only consumes three ASCII characters, a leading space is provided in
the data field.
Offset: 2Dh-2Eh
Bit Description
15:0 Minimum Cache Voltage
0000h-0321h: Reserved
0322: 0.802 V
0323h-FFFFh: Reserved
Offset: 2Fh-30h
Bit Description
15:0 RESERVED 4
0000h-FFFFh: Reserved
Offset: 31h
Bit Description
7:0 Cache Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value