Datasheet

Features
102 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
7.4.3.4.2 L2SIZE: L2 Cache Size
This location contains the size of the level two cache in kilobytes. Writes to this register
have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series has a 2 MB (2048 KB) L2
cache total (1 MB L2 cache per core). Thus, offset 27 - 28h will contain 0800h.
7.4.3.4.3 L3SIZE: L3 Cache Size
This location contains the size of the level three cache in kilobytes. Writes to this
register have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series has either a 4 MB
(4096 KB), 8 MB (8192 KB) or 16 MB (16384 KB) L3 cache. Thus, offset 29 - 2Ah will
contain 1000h (for 4 MB), 2000h (for 8 MB) or 4000h (for 16 MB).
7.4.3.4.4 MAXCVID: Maximum Cache VID
This location contains the maximum Cache VID (Voltage Identification) voltage that
may be requested via the CVID pins. This field, rounded to the next thousandth, is in
mV and is reflected in hex. Writes to this register have no effect.
Example: From Ta b le 2- 1 0 the maximum CVID is 1.3500 V maximum voltage. Offset
2B - 2Ch would contain 0546h (1350 decimal).
Offset: 27h-28h
Bit Description
15:0 L2 Cache Size
0000h-07FFh: Reserved
0800h: 2 MB
0801h-FFFFh: Reserved
Offset: 29h-2Ah
Bit Description
15:0 L3 Cache Size
0000h-0FFFh: Reserved
1000h: 4MB
1001h-1FFFh: Reserved
2000h: 8MB
2001h-3FFFh: Reserved
4000h: 16MB
4001h-FFFFh: Reserved
Offset: 2Bh-2Ch
Bit Description
15:0 Maximum Cache VID
0000h-0545h: Reserved
0546h: 1.35 V
0548h-FFFFh: Reserved