Datasheet

Summary Tables of Changes
Specification Update 13
Stepping Number
C0 D0 Dual Core
Only
Plans ERRATA
AE40 X X No Fix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
AE41 X X X No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AE42 X X X No Fix
Simultaneous Access to the Same Page Table Entries by Both
Cores May Lead to Unexpected Processor Behavior
AE43 X X Fixed IO_SMI Indication in SMRAM State Save Area May Be Lost
AE44 X X X No Fix
Logical Processors May Not Detect Write-Back (WB) Memory
Writes
AE45 X X No Fix Last Exception Record (LER) MSRs May Be Incorrectly Updated
AE46 X X No Fix
SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null
Segment Selector” to SS and CS Registers
AE47 X X No Fix
Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
AE48 X X No Fix
Using 2-M/4-M pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AE49 X X X No Fix
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon
(Architectural Performance Monitoring) Specification
AE50 X X No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AE51 X X No Fix
Performance Monitoring Events for Retired Instructions (C0H)
May Not Be Accurate
AE52 X X No Fix
#GP Fault Is Not Generated on Writing IA32_MISC_ENABLE
[34] When Execute Disable Bit Is Not Supported
AE53 X X X No Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without
T
LB Shootdown May Cause Unexpected
Processor Behavior
AE54 X X No Fix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code
(SMC) Event May Cause Unexpected Behavior
AE55 X X X No Fix Shutdown Condition May Disable Non-Bootstrap Processors
AE56 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AE57 X X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a Memory
Ordering Issue
AE58 X X No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect
Data after a Machine Check Exception (MCE)
AE59 X X No Fix
Using Memory Type Aliasing with Memory Types WB/WT May
Lead to Unpredictable Behavior