Datasheet

Errata
Specification Update 59
AR103 RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Problem: RSM instruction execution, under certain conditions triggered by a complex sequence
of internal processor micro-architectural events, may lead to processor hang, or
unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM instruction may
restart the interrupted processor context through a nondeterministic EIP offset in the
code segment, resulting in unexpected instruction execution, unexpected exceptions
or system hang. Intel has not observed this erratum with any commercially available
software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Please contact
your Intel sales representative for availability.
Status: For the steppings affected, see the Summary Tables of Changes.
AR104 NMIs May Not Be Blocked by a VM-Entry Failure
Problem: The Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3B:
System Programming Guide, Part 2 specifies that, following a VM-entry failure during
or after loading guest state, “the state of blocking by NMI is what it was before VM
entry.” If non-maskable interrupts (NMIs) are blocked and the “virtual NMIs” VM-
execution control set to 1, this erratum may result in NMIs not being blocked after a
VM-entry failure during or after loading guest state.
Implication: VM-entry failures that cause NMIs to become unblocked may cause the processor to
deliver an NMI to software that is not prepared for it.
Workaround: VMM software should configure the virtual-machine control structure (VMCS) so that
VM-entry failures do not occur.
Status: For the steppings affected, see the Summary Tables of Changes.