Datasheet

Errata
58 Specification Update
AR101. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
Problem: Under certain conditions, as described in the Intel® 64 and IA-32 Architecture
Software Developer’s Manual, section "Out-of-Order Stores For String Operations in
Pentium 4, Intel Xeon, and P6 Family Processors", the processor may perform REP
MOVS or REP STOS as write combining stores (referred to as “fast strings”) for
optimal performance. FXSAVE may also be internally implemented using write
combining stores. Due to this erratum, stores of a WB (write back) memory type to a
cache line previously written by a preceding fast string/FXSAVE instruction may be
observed before string/FXSAVE stores.
Implication: A write-back store may be observed before a previous string or FXSAVE related store.
Intel has not observed this erratum with any commercially available software.
Workaround: Software desiring strict ordering of string/FXSAVE operations relative to subsequent
write-back stores should add an MFENCE or SFENCE instruction between the
string/FXSAVE operation and following store-order sensitive code such as that used for
synchronization.
Status: For the steppings affected, see the Summary Tables of Changes.
AR102. Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory types. Memory type aliasing
with a cacheable memory type and WC (write combining) may cause the processor to
perform incorrect operations leading to memory ordering violations for WC
operations.
Implication: Software that uses aliasing between cacheable and WC memory types may observe
memory ordering errors within WC memory operations. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified. Intel does not support the use of cacheable and WC memory type
aliasing, and WC operations are defined as weakly ordered.
Status: For the steppings affected, see the Summary Tables of Changes.