Datasheet

Errata
56 Specification Update
AR96. PMI While LBR Freeze Enabled May Result in Old/Out-of-Date LBR
Information
Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance
Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch Record
(LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag (bit 11) to 1 in
IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon the occurrence of a
hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e.,
before the hardware PMI request).
Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR
information that does not describe the last few branches before the PEBS sample that
triggered the PMI.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AR97. BIST Failure after Reset
Problem: The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX
register when coming out of reset.
Implication:
When this erratum occurs, an erroneous BIST failure will be reported in EAX
bit [17]. This failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX
register after coming out of reset.
Status: For the steppings affected, see the Summary Tables of Changes.