Datasheet

Errata
54 Specification Update
AR90. Store Ordering May Be Incorrect between WC and WP Memory Types
Problem: According to Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume
3A: System Programming Guide, WP (Write Protected) stores should drain the WC
(Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.
AR91. Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Instructions as Branches
Problem: Performance monitoring event BR_INST_RETIRED (C4H) counts retired branch
instructions. Due to this erratum, two of its sub-events mistakenly count for CPUID
instructions as well. Those sub events are: BR_INST_RETIRED.PRED_NOT_TAKEN
(Umask 01H) and BR_INST_RETIRED.ANY (Umask 00H).
Implication: The count value returned by the performance monitoring event
BR_INST_RETIRED.PRED_NOT_TAKEN or BR_INST_RETIRED.ANY may be higher than
expected. The extent of over counting depends on the occurrence of CPUID
instructions, while the counter is active.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR92. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the
number of memory accesses that cross an 8-byte boundary and are blocked until
retirement. Due to this erratum, the performance monitoring event
MISALIGN_MEM_REF also counts other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent
of the over counting depends on the number of memory accesses retiring while the
counter is active.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.