Datasheet

Errata
Specification Update 53
AR88. Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of
the following conditions are met:
• A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
• Code execution transitions to a different code page such that both
⎯ The target linear address corresponds to the modified PDE
⎯ The PTE (Page Table Entry) for the target linear address has an A (Accessed)
bit that is clear
• One of the following simultaneous exception conditions is present following the
code transition
⎯ Code #DB and code #PF
⎯ Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR89. Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating Frequency
Problem: Performance Counter MSR_PERF_FIXED_CTR2 (MSR 30BH) that counts
CPU_CLK_UNHALTED.REF clocks should count these clock cycles at a constant rate
that is determined by the maximum resolved boot frequency, as programmed by
BIOS. Due to this erratum, the rate is instead set by the maximum core-clock to bus-
clock ratio of the processor, as indicated by hardware.
Implication: No functional impact as a result of this erratum. If the maximum resolved boot
frequency as programmed by BIOS is different from the frequency implied by the
maximum core-clock to bus-clock ratio of the processor as indicated by hardware,
then the following effects may be observed:
Workaround: Performance Monitoring Event CPU_CLK_UNHALTED.REF will count at a rate different
than the TSC (Time Stamp Counter)
Workaround: When running a system with several processors that have different maximum core-
clock to bus-clock ratios, CPU_CLK_UNHALTED.REF monitoring events at each
processor will be counted at different rates and therefore will not be comparable.
Workaround: Calculate the ratio of the rates at which the TSC and the CPU_CLK_UNHALTED.REF
performance monitoring event count (this can be done by measuring simultaneously
their counted value while executing code) and adjust the CPU_CLK_UNHALTED.REF
event count to the maximum resolved boot frequency using this ratio.
Status: For the steppings affected, see the Summary Tables of Changes.