Datasheet

Errata
Specification Update 49
AR77. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of
the resultant stack frame may contain unexpected values (i.e., residual stack data as
a result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Please refer to "Procedure Calls For Block-Structured Languages" in the
Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 1: Basic
Architecture, for information on the usage of the ENTER instructions. This erratum is
not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch
occurs when transferring to ring 0. Intel has not observed this erratum on any
commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR78. Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
Problem: When an unaligned access is performed on paging structure entries, accessing a
portion of two different entries simultaneously, the processor may live lock.
Implication: When this erratum occurs, the processor may live lock causing a system hang.
Workaround: Do not perform unaligned accesses on paging structure entries.
Status: For the steppings affected, see the Summary Tables of Changes.
AR79. INVLPG Operation for Large (2M/4M) Pages May Be Incomplete
under Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
(TLB) entries for large pages (2-M/4-M) when both of the following conditions exist:
• Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified.
• INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an access
that results in either A or D bits being set in a Page Table Entry (PTE)
Implication: Stale translations may remain valid in TLB after a PTE update resulting in
unpredictable system behavior. Intel has not observed this erratum with any
commercially available software
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for
the entire address range of the large page.
Status: For the steppings affected, see the Summary Tables of Changes.