Datasheet

Errata
46 Specification Update
AR68. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint
Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly
cleared when the following sequence happens:
1. POP instruction to SS (Stack Segment) selector.
2. Next instruction is FP (Floating Point) that gets FP assist followed by code
breakpoint.
Implication: B0-B3 bits in DR6 may not be properly cleared.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR69. BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a
software interrupt may result in the overwriting of BTM/BTS branch-from instruction
address by the LBR (Last Branch Record) branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR70. REP Store Instructions in a Specific Situation may cause the
Processor to Hang
Problem: During a series of REP (repeat) store instructions a store may try to dispatch to
memory prior to the actual completion of the instruction. This behavior depends on
the execution order of the instructions, the timing of a speculative jump and the
timing of an uncacheable memory store. All types of REP store instructions are
affected by this erratum.
Implication: When this erratum occurs, the processor may live lock and/or result in a system hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.