Datasheet

Errata
Specification Update 45
AR65. PEBS Buffer Overflow Status Will Not Be Indicated Unless
IA32_DEBUGCTL[12] is Set
Problem: IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a PEBS
(Precise Event-Based Sampling) overflow has occurred and a PMI (Performance
Monitor Interrupt) has been sent. Due to this erratum, this bit is not set unless
IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all performance monitor counters
upon a PMI) is also set.
Implication: Due to this erratum, IA32_PERF_GLOBAL_STATUS [62] will not signal that a PMI was
generated due to a PEBS Overflow unless IA32_DEBUGCTL [12] is set.
Workaround: It is possible for the software to set IA32_DEBUGCTL [12] to avoid this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AR66. The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8)
of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the
following:
• DR7 GD (General Detect, bit 13) being bit set
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AR67. An Asynchronous MCE during a Far Transfer May Corrupt ESP
Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR
RET or IRET and in the presence of certain internal conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, for example when the CPL (Current
Privilege Level) was changed or when going through an interrupt task gate, then the
corrupted ESP will be saved on the stack or in the TSS (Task State Segment), and will
not be used.
Workaround: Use an interrupt task gate for the machine check handler.
Status: For the steppings affected, see the Summary Tables of Changes.