Datasheet

Errata
Specification Update 37
AR47. Code Breakpoint May Be Taken after POP SS Instruction If It Is
followed by an Instruction That Faults
Problem: A POP SS instruction should inhibit all interrupts including Code Breakpoints until after
execution of the following instruction. This allows sequential execution of POP SS and
MOV eSP, eBP instructions without having an invalid stack during interrupt handling.
However, a code breakpoint may be taken after POP SS if it is followed by an
instruction that faults, this result in a code breakpoint being reported on an
unexpected instruction boundary since both instructions should be atomic.
Implication: This can result in a mismatched Stack Segment and SP. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: As recommended in the Intel® 64 and IA-32 Architecture Software Developer’s
Manual, the use "POP SS" in conjunction with "MOV eSP, eBP" will avoid the failure
since the "MOV" will not fault.
Status: For the steppings affected, see the Summary Tables of Changes.
AR48. Last Branch Records (LBR) Updates May Be Incorrect after a Task
Switch
Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to
the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.